參數(shù)資料
型號: DS87C550
廠商: Maxim Integrated Products, Inc.
英文描述: EPROM High-Speed Micro with A/D and PWM(帶 A/D 和 PWM的EPROM/ROM高速微控制器)
中文描述: 存儲(chǔ)器高速微與A / D及PWM(帶A / D轉(zhuǎn)換和脈寬調(diào)制的存儲(chǔ)器/ ROM的高速微控制器)
文件頁數(shù): 4/27頁
文件大小: 119K
代理商: DS87C550
APPLICATION NOTE 78
030998 4/27
ENTERING AND EXITING POWER
MANAGEMENT MODES
Software invokes the desired power management
mode using bits in the Power Management Register
(PMR). Stop mode is invoked by setting the STOP bit
(PCON.1). The device speed is selected by the clock
divider rate bits CD1, CD0 (PMR.7–6), shown below.
CLOCK DIVISOR RATE BIT SETTINGS
CD1
CD0
MACHINE CYCLE RATE
0
0
Reserved
0
1
4 clocks (default)
1
0
64 clocks (PMM1)
1
1
1024 clocks (PMM2)
PMM1 and PMM2 can be exited by configuring the clock
divider rate bits CD1, CD0, or by the switchback func-
tion. Entry to or exit from either PMM can only be via the
divide by 4 mode. For example, to go from PMM1 (divide
by 64) to PMM2 (divide by 1024) mode, it is necessary to
first switch from PMM1 to divide by 4 mode, and then
from divide by 4 to PMM2. Attempts to execute an illegal
speed change will be ignored and the bits will remain
unchanged. It is the responsibility of the software to test
for serial port activity using the Status register (STA-
TUS;C5h) before attempting to change speed. Chang-
ing speed during an asynchronous serial port operation
will corrupt the serial transmission.
When PMM is invoked, the external crystal will continue
to operate at full speed, and the DS87C5x0 will still
execute four internal states per machine cycle. In PMM
the device performs an internal divide of the external
clock, by 16 for PMM1 (16 x 4=64) or 256 for PMM2
(256 x 4=1024) to achieve the desired frequency, as
opposed to actually performing 64 or 256 internal states
per instruction. For example, operations that occur dur-
ing C2 will still do so. Most applications will not find it
necessary to attend to this much detail, but the informa-
tion is provided for calculating critical timings.
INTERNAL TIMING RELATIONSHIPS IN PMM1
Figure 2
C1
C2
C3
C4
C1
C2
MACHINE
ALE
INTERNAL
CLOCK
EXTERNAL
CLOCK
64 CLOCK CYCLES
SINGLE–CYCLE INSTRUCTION
MACHINE CYCLE
MACHINE CYCLE
SINGLE–CYCLE
INSTRUCTION
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