________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Rev: 063008
102 of 375
Figure 9-3. Example Functional Timing: DS2155 T1 Transmit-Side Boundary Timing
* Note DS2155 TCLK shown only for comparative purposes.
Figure 9-4. Example Functional Timing: DS2155 E1 Receive-Side Boundary Timing
* Note DS2155 RCLK shown only for comparative purposes.
Figure 9-5. Example Functional Timing: DS2155 T1 Receive-Side Boundary Timing
* Note DS2155 RCLK shown only for comparative purposes.
When interfacing to a Maxim T1/E1 transceiver as shown, the device should be programmed to invert the RCLK
input for each serial interface (
LI.RCR1.RCLKINV = 1).
Because the first gapped transmit clock input edge after the transmit sync pulse is coincident with the start of the
first byte of user data, the transmit sync setup control bits must be configured for a sync pulse that arrives zero
LSB
X
MSB
LSB MSB
TIME SLOT 1
TIME SLOT 2
TCLK
TSER
TSYNC
TCHCLK
CHANNEL 32
FRAMING BYTE / CHANNEL 0
CHANNEL 1
RCLK
RSER
RSYNC
LSB
MSB
LSB
RCHCLK
TIME SLOT 24
TIME SLOT 1
TIME SLOT 2
RCLK
RSER
RSYNC
LSB
MSB
LSB
RCHCLK
F