________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Rev: 063008
23 of 375
PACKAGE PINS
NAME
256
144
TYPE
FUNCTION
GMII/MII/RMII PORT
TXD[0]/TXD1[0],
TXD[1]/TXD1[1],
TXD[2]/TXD1[2],
TXD[3]/TXD1[3],
TXD[4]/TXD2[0],
TXD[5]/TXD2[1],
TXD[6]/TXD2[2],
TXD[7]/TXD2[3]
J13,
K15,
J15,
H13,
N15,
P15,
R15,
T15
J8,
J9,
H8,
H9,
L8,
K8,
L9,
K9
O
Transmit Data 0 through 7(GMII Mode). TXD[0:7] is presented
synchronously with the rising edge of TX_CLK1. TXD[0] is the least
significant bit of the data. When TX_EN1 is low the data on TXD should
be ignored.
MAC 1 Transmit Data 0 through 3(MII Mode – TXD1[0:3]). Four bits of
data TXD1[0:3] presented synchronously with the rising edge of
TX_CLK1.
MAC 1 Transmit Data 0 through 1(RMII Mode – TXD1[0:1]). Two bits of
data TXD1[0:1] presented synchronously with the rising edge of
TX_CLK1.
MAC 2 Transmit Data 0 through 3(MII Mode– TXD2[0:3]).Four bits of
data TXD2[0:3] presented synchronously with the rising edge of
TX_CLK2. Note that TXD2[0:3] is only available on devices with two
Ethernet ports.
MAC 2 Transmit Data 0 through 1(RMII Mode– TXD2[0:1]). Two bits of
data TXD2[0:1] presented synchronously with the rising edge of
TX_CLK2. Note that TXD2[0:1] is only available on devices with two
Ethernet ports.
RXD[0]/RXD1[0],
RXD[1]/RXD1[1],
RXD[2]/RXD1[2],
RXD[3]/RXD1[3],
RXD[4]/RXD2[0],
RXD[5]/RXD2[1],
RXD[6]/RXD2[2],
RXD[7]/RXD2[3]
G14,
F13,
F14,
H14,
N16,
M16,
L15,
K16
J10,
J11,
H10,
H11,
L10,
L11,
K10,
K11
I
MAC 1 Receive Data 0 through 7(GMII Mode). Eight bits of received
data, sampled synchronously with the rising edge of RX_CLK. For every
clock cycle, the PHY transfers 8 bits to the device. RXD[0] is the least
significant bit of the data. Data is not considered valid when RX_DV is
low.
MAC 1 Receive Data 0 through 3(MII Mode – RXD1[0:3]). Four bits of
received data, sampled synchronously with RX_CLK1. Accepted when
RX_CRS1 is asserted.
MAC 1 Receive Data 0 through 1(RMII Mode – RXD1[0:1]). Two bits of
received data, sampled synchronously with RX_CLK1. Accepted when
RX_CRS1 is asserted.
MAC 2 Receive Data 0 through 3(MII Mode – RXD2[0:3]): Four bits of
received data, sampled synchronously with RX_CLK2. Accepted when
RX_CRS2 is asserted.
MAC 2 Receive Data 0 through 1(RMII Mode – RXD2[0:1]). Two bits of
received data, sampled synchronously with RX_CLK2. Accepted when
RX_CRS2 is asserted.
RX_CLK1,
RX_CLK2
G16,
N13
J12
IO
Receive Clock 1 (GMII). 125MHz clock. This clock is used to sample the
RXD[7:0] data.
Receive Clock 1 (MII). Timing reference for RX_DV, RX_ERR and
RXD[3:0], which are clocked on the rising edge. RX_CLK frequency is
25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. In DTE
mode, this is a clock input provided by the PHY.
Receive Clock 2 (MII Only). Timing reference for RX_DV2, RX_ERR2 and
RXD2[3:0], which are clocked on the rising edge. RX_CLK2 frequency is
25MHz for 100Mbps operation and 2.5MHz for 10Mbps operation. In DTE
mode, this is a clock input provided by the PHY. Note that RX_CLK2 is
only available on devices with two Ethernet ports.
TX_CLK1,
TX_CLK2
M15,
T16
L12
IO
Transmit Clock 1 (MII). Timing reference for TX_EN1 and TXD1[3:0].
The TX_CLK1 frequency is 25MHz for 100Mbps operation and 2.5MHz
for 10Mbps operation. In DTE mode, this is a clock input provided by the
PHY. Sourced from REF_CLK Input.
Transmit Clock 2 (MII Only). Timing reference for TX_EN2 and TXD2[3:0].
The TX_CLK2 frequency is 25MHz for 100Mbps operation and 2.5MHz
for 10Mbps operation. In DTE mode, this is a clock input provided by the
PHY. Note that TX_CLK2 is only available on devices with two Ethernet
ports. Sourced from REF_CLK Input.