________________________________________________ DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Rev: 063008
31 of 375
Figure 7-1. 256-Ball, 17mm x 17mm CSBGA Pinout (DS33X162/X161/X82/X81/X42/X41)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
JTCLK
SDA[3]
SDA[10]
SDCS
SDA[12]
SRAS
SWE
SD_CLK
VSS
VDDQ
SDATA[6] SDATA[4]
VDDQ
B
JTRST
SDA[2]
SBA[1]
SBA[0]
SDA[6]
SDA[9]
SCAS
VDD2.5
VREF
SDATA[12] SDATA[13] SDATA[15] SDATA[7]
VSSQ
SDATA[2] SDATA[1]
C
JTMS
SDA[1]
SDA[0]
SD_CLKE
N
SDA[7]
SDA[11]
VSS
VSSQ
SDATA[9] SDATA[11] SDATA[14] SDATA[5] SD_LDQS
VDDQ
SDATA[3] SDATA[0]
D
RDATA1
JTDI
SDA[4]
SDA[5]
SDA[8]
VSSQ
SD_UDM SD_UDQS SDATA[8]
VDDQ
VDD1.8 SDATA[10] SD_LDM
VDDQ
VSSQ
E
RCLK1
JTDO
VDD1.8
VDD2.5
VSSQ
VDD2.5
RST
VDD3.3
AVSS
VDD3.3
RX_CRS1
COL1
VSSQ
SYSCLKI
F
RSYNC1
RDATA6
RDATA5
RCLK5
AVDD
VSS
VDD3.3
VSS
VDD1.8
RXD[1] /
RXD1[1]
RXD[2] /
RXD1[2]
MDC
VSS
G
RCLK3
RSYNC3
RSYNC5
RDATA3
VDD3.3
VSS
RCLK2
RDATA2
VSS
A8
A10
VDD1.8
MDIO
RXD[0] /
RXD1[0]
RX_DV1
RX_CLK1
H
RSYNC4
RDATA4
RSYNC6
RCLK4
VSS
DNC
RSYNC2
DNC
VSS
VDD1.8
TXD[3] /
TXD1[3]
RXD[3] /
RXD1[3]
RX_ERR1
HIZ
J
RCLK6
RCLK10
RCLK9
RCLK8
RCLK7
DNC
ALE
CS
RD / DS
WR / RW
INT
MODE
TXD[0] /
TXD1[0]
RX_CRS2
TXD[2] /
TXD1[2]
SPI_SEL
K
RDATA7
RDATA9 RDATA10 RSYNC9
VDD3.3
D0 /
SPI_MISO
D2 /
SPI_CLK
D4
D6 /
SPI_CPHA
A0
A2
A6
A4
TX_EN1
TXD[1] /
TXD1[1]
RXD[7] /
RXD2[3]
L
RDATA8
RSYNC8 RSYNC11 RDATA12
RCLK13
D1 /
SPI_MOSI
D3
D5 /SPI_
SWAP
A1
A3
A5
A7
A9
TX_ERR1
RXD[6] /
RXD2[2]
COL2
M RSYNC10 RCLK11
VDD1.8
RSYNC13 TDATA5
TSYNC3
TCLK5
VDD3.3
D7 /
SPI_CPOL
TMCLK4
RX_DV2 RX_ERR2
VSS
RMII_SEL TX_CLK1
RXD[5] /
RXD2[1]
N
RDATA11
RCLK12
RDATA15 RDATA16 RSYNC7
TDATA6
TDATA7
TSYNC7
TDATA4
TDATA9
TDATA11 TDATA15 RX_CLK2 TMSYNC4
TXD[4] /
TXD2[0]
RXD[4] /
RXD2[0]
P
RSYNC12 RDATA13 RSYNC15
VDD3.3
TCLK2
TDATA3
TSYNC4
TSYNC6
TCLK4
TCLK6
TDATA16 TDATA14 DCEDTES TDATA13
TXD[5] /
TXD2[1]
TX_EN2
R
RDATA14 RSYNC14 RCLK16
VSS
TCLK1
TSYNC1
TSYNC5
TCLK3
TDATA8
TCLK8
TDATA10 TDATA12
VDD1.8
GTX_CLK
TXD[6] /
TXD2[2]
TX_ERR2
T
RCLK14
DNC
RSYNC16 RCLK15
VSS
TDATA1
TDATA2
TSYNC2
TSYNC8
TCLK7
TMCLK3 TMSYNC3 REF_CLK
VDD3.3
TXD[7] /
TXD2[3]
TX_CLK2
Note: Shaded pins do not apply to all devices in the product family. See the pin listing for specific pin availability. In the high port
count devices, the shaded input pins DO NOT HAVE PULLUP/PUL-DOWN resistors. Consideration must be taken during board
design to bias the inputs appropriately, and to float output pins (TDATA5-TDATA16, TX_EN2, TX_ERR2) if lower port count
designs are to be potentially stuffed with higher port count devices.