參數(shù)資料
型號： DS3254DK
廠商： Maxim Integrated Products
文件頁數(shù)： 45/71頁
文件大?。?/td> 0K
描述： KIT DEMO FOR DS3254
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設計資源： DS3254DK Gerber Files
標準包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS3254
已供物品： 板，CD
DS3251/DS3252/DS3253/DS3254
5 of 71
FEATURES (CONTINUED)
Receiver
AGC/equalizer block handles from 0 to 15dB of cable loss
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Optional B3ZS/HDB3 decoder
Line-code violation output pin and counter
Binary or bipolar framer interface
On-board 2
15 - 1 and 223 - 1 PRBS detector
Clock inversion for glueless interfacing
Tri-state clock and data outputs support protection switching applications
Per-channel power-down control
Transmitter
Binary or bipolar framer interface
Gapped clock capable up to 51.84MHz
Wide 50
± 20% transmit clock duty cycle
Clock inversion for glueless interfacing
Optional B3ZS/HDB3 encoder
On-board 2
15 - 1 and 223 - 1 PRBS generator
Complete DS3 AIS generator (ANSI T1.107)
Unframed all-ones generator (E3 AIS)
Line build-out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor
Jitter Attenuator
On-chip crystal-less jitter attenuator
Meets all applicable ANSI, ITU, ETSI and Telcordia jitter transfer and output jitter requirements
Can be placed in the transmit path, receive path or disabled
Selectable FIFO depth: 16, 32, 64 or 128 bits
Overflow and underflow status indications
Clock Adapter
Operates from a single DS3, E3, STS-1, 19.44 MHz, 38.88 MHz, or 77.76 MHz master clock
Synthesizes clock rates that are not provided externally
Use of common system timing frequencies such as 19.44 MHz eliminates the need for any local oscillators,
reduces cost and board space
Very small jitter gain and intrinsic jitter generation
Optionally provides synthesized clocks on output pins for use by neighboring components, such as framers or
mappers
Parallel CPU Interface
Multiplexed or nonmultiplexed 8-bit interface
Configurable for Intel mode (
CS, WR, RD) or Motorola mode (CS, DS, R/W)
SPI CPU Interface
Operation up to 10 Mbit/s
Burst mode for multi-byte read and write accesses
Programmable clock polarity and phase
Half-duplex operation gives option to tie SDI and SDO together externally to reduce wire count
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相關代理商/技術參數(shù)
參數(shù)描述
DS3254N 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254N# 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254N+ 功能描述:網(wǎng)絡控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254NA3 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube
DS3256 功能描述:網(wǎng)絡控制器與處理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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