Note: These pins are active in hardware mode. NAME TYPE FUNCTION" />
參數(shù)資料
型號： DS3254DK
廠商： Maxim Integrated Products
文件頁數(shù)： 4/71頁
文件大?。?/td> 0K
描述： KIT DEMO FOR DS3254
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
設(shè)計資源： DS3254DK Gerber Files
標準包裝： 1
主要目的： 電信，線路接口單元（LIU）
已用 IC / 零件： DS3254
已供物品： 板，CD
DS3251/DS3252/DS3253/DS3254
12 of 71
Table 6-D. Hardware Mode Pin Descriptions
Note: These pins are active in hardware mode.
NAME
FUNCTION
E3Mn
I
E3 Mode Enable
0 = DS3 operation
1 = E3 or STS-1 operation
STSn
I
STS-1 Mode Enable
When E3M = 1,
0 = E3 operation
1 = STS-1 operation
When E3M = 0, STS selects the DS3 AIS pattern. See Table 6-G.
LLBn,
RLBn
I
Local Loopback Select, Remote Loopback Select
{LLB, RLB} =
00 = no loopback
01 = remote loopback
10 = analog local loopback
11 = digital local loopback
RBIN
I
Receiver Binary Framer-Interface Enable
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is
disabled.
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code
violations. The B3ZS/HDB3 encoder is enabled.
RCINV
I
Receiver Clock Invert
0 = RPOS/RDAT and RNEG/RLCV update on the falling edge of RCLK.
1 = RPOS/RDAT and RNEG/RLCV update on the rising edge of RCLK.
RJAn
I
Receiver Jitter Attenuator Enable
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
See Table 6-I for more information.
RMONn
I
Receive Monitor-Preamp Enable. RMON determines whether or not the receiver’s preamp is enabled
to provide flat gain to the incoming signal before the AGC/equalizer block processes it. This feature
should be enabled when the device is being used to monitor signals that have been resistively
attenuated by a monitor jack. See Section 8.2 for more information.
0 = disable the monitor preamp
1 = enable the monitor preamp
TBIN
I
Transmitter Binary Framer-Interface Enable
0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder is
disabled.
1 = Transmitter framer interface is binary on the TDAT pin. (TNEG is ignored and should be wired low.)
The B3ZS/HDB3 encoder is enabled.
TCINV
I
Transmitter Clock Invert
0 = TPOS/TDAT and TNEG are sampled on the rising edge of TCLK.
1 = TPOS/TDAT and TNEG are sampled on the falling edge of TCLK.
TDSAn,
TDSBn
I
Transmitter Data Select. These inputs select the source of the transmit data. See Table 6-G for
details.
TJAn
I
Transmitter Jitter Attenuator Enable
0 = remove jitter attenuator from the transmitter path
1 = insert jitter attenuator into the transmitter path
See Table 6-I for more information.
TLBOn
I
Transmitter Line Build-Out Enable. TLBO indicates cable length for waveform shaping in DS3 and
STS-1 modes. TLBO is ignored for E3 mode and should be wired high or low.
0 = cable length
≥ 225ft
1 = cable length < 225ft
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3254N 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254N# 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3254NA3 制造商:Maxim Integrated Products 功能描述:QUAD ENH DS3/E3 LIU REV A3 IND - Rail/Tube
DS3256 功能描述:網(wǎng)絡(luò)控制器與處理器 IC X6 T3/E3 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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