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| 型號(hào)： | DS3184N+ |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 82/400頁(yè) |
| 文件大小： | 0K |
| 描述： | IC PACKET PHY W/LIU 400-CSBGA |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 類(lèi)型： | 調(diào)幀器 |
| 應(yīng)用： | 數(shù)據(jù)傳輸 |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 400-BBGA |
| 供應(yīng)商設(shè)備封裝： | 400-PBGA（27x27） |
| 包裝： | 管件 |
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DS3181/DS3182/DS3183/DS3184
172
10.10.6.2 Transmit M23 DS3 Frame Generation
M23 DS3 frame generation receives the incoming payload data stream, and overwrites the entire DS3 overhead bit
locations.
The multiframe alignment bits (M1, M2, and M3) are overwritten with the values zero, one, and zero (010)
respectively.
The sub-frame alignment bits (FX1, FX2, FX3, and FX4) are overwritten with the values one, zero, zero, and one
(1001) respectively.
The X-bits (X1 and X2) are both overwritten with the Remote Defect Indicator (RDI). The RDI source is
programmable (automatic, 1, or 0). If the T3.TCR.ARDID is one then the T3.TCR.TRDI register bit controls this bit.
If the RDI is generated automatically (T3.TCR.ARDID=0), the X-bits are set to zero when one or more of the
indicated alarm conditions is present, and set to one when all of the indicated alarm conditions are absent.
Automatically setting RDI on LOS, SEF, LOF, or AIS is individually programmable (on or off).
The P-bits (P1 and P2) are both overwritten with the calculated payload parity from the previous DS3 frame. The
payload parity is calculated by performing modulo 2 addition of all of the payload bits after all frame processing has
been completed. P-bit generation is programmable (on or off). The P-bits will be generated if either P-bit generation
is enabled or frame generation is enabled.
If C-bit generation is enabled (T3.TCR.CBGD), the bit C11 is overwritten with an alternating one zero pattern, and
all of the other C-bits (CXY) are overwritten with zeros. If C-bit generation is disabled, then all of the C-bit timeslots
(CXY) will be treated as payload data, and passed through. C-bit generation is programmable (on or off). Note:
Overhead insertion may still overwrite the C-bit time slots even if C-bit generation is disabled.
Once all of the DS3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming DS3 signal is passed on directly to error insertion. Frame generation is
programmable (on or off). Note: P-bit generation may still be performed even if frame generation is disabled.
10.10.6.3 Transmit M23 DS3 Error Insertion
Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be
inserted are framing errors and P-bit parity errors.
The framing error insertion mode is programmable (F-bit, M-bit, SEF, or OOMF). An F-bit error is a single sub-
frame alignment bit (FXY) error. An M-bit error is a single multiframe alignment bit (M1, M2, or M3) error. An SEF
error is an error in all the sub-frame alignment bits in a sub-frame (FX1, FX2, FX3, and FX4). An OOMF error is a
single multiframe alignment bit (M1, M2, or M3) error in each of two consecutive DS3 frames.
A P-bit parity error is generated by is inverting the value of the P-bits (P1 and P2) in a single DS3 frame. P-bit parity
error(s) can be inserted one error at a time, or continuously. The P-bit parity error insertion mode (single or
continuous) is programmable.
Each error type (framing or P-bit parity) has a separate enable. Continuous error insertion mode inserts errors at
every opportunity. Single error insertion mode inserts an error at the next opportunity when requested. The framing
multi-error insertion modes (SEF or OOMF) insert the indicated number of error(s) at the next opportunities when
requested; i.e., a single request will cause multiple errors to be inserts. The requests can be initiated by a register
bit (TSEI) or by the manual error insertion input (TMEI). The error insertion request source (register or input) is
programmable. The insertion of each particular error type is individually enabled. Once all error insertion has been
performed, the data stream is passed on to overhead insertion.
10.10.6.4 Transmit M23 DS3 Overhead Insertion
Overhead insertion can insert any (or all) of the DS3 overhead bits into the DS3 frame. The DS3 overhead bits X1,
X2, P1, P2, MX, FXY, and CXY can be sourced from the transmit overhead interface (TOHCLK, TOH, TOHEN, and
TOHSOF). The P-bits (P1 and P2) are received as an error mask (modulo 2 addition of the input bit and the
internally generated bit). The DS3 overhead insertion is fully controlled by the transmit overhead interface. If the
transmit overhead data enable signal (TOHEN) is driven high, then the bit on the transmit overhead signal (TOH) is
inserted into the output data stream. Insertion of bits using the TOH signal overwrites internal overhead insertion.
相關(guān)PDF資料 |
PDF描述 |
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| DS3184+ | IC PACKET PHY W/LIU 400-CSBGA |
| MAX4507CWN | IC SIGNAL LINE PROTECTOR 18-SOIC |
| MAX4507CAP | IC SIGNAL LINE PROTECTOR 20-SSOP |
| LFXP20C-4F484I | IC FPGA 19.7KLUTS 340I/O 484-BGA |
| MAX4505EUK-T | IC SIGNAL LINE PROTECTOR SOT23-5 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3184N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad ATM/Packet PHYs w/Built-In LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS318PIN | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Industrial Control IC |
| DS-318PIN | 制造商:MA-COM 制造商全稱(chēng):M/A-COM Technology Solutions, Inc. 功能描述:Plug-In Two-Way Power Divider, 5 - 500 MHz |
| DS-318-PIN | 功能描述:信號(hào)調(diào)節(jié) RoHS:否 制造商:EPCOS 產(chǎn)品:Duplexers 頻率:782 MHz, 751 MHz 頻率范圍: 電壓額定值: 帶寬: 阻抗:50 Ohms 端接類(lèi)型:SMD/SMT 封裝 / 箱體:2.5 mm x 2 mm 工作溫度范圍:- 30 C to + 85 C 封裝:Reel |
| DS319 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Two-Way Power Divider 10500 MHz |
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