DS3181/DS3182/DS3183/DS3184
389
Table 18-6. System Interface L3 Timing
(VDD = 3.3V ±5%, Tj = -40°C to +125°C.)
SIGNAL NAME(S)
SYMBOL
DESCRIPTION
MIN
TYP
MAX UNITS
RSCLK and TSCLK
f1
Clock frequency (1/t1) (Note 1)
0
66
MHz
RSCLK and TSCLK
t2/t1
Clock duty cycle (Note 1)
40
50
60
%
RSCLK and TSCLK
t3
Rise/fall times (Notes 1, 2)
2
ns
RADR and
REN
t5
Hold time from RSCLK (Note 1)
0
ns
RADR and
REN
t6
Setup time to RSCLK (Note 1)
3.5
ns
RDATA, RPRTY, RPXA,
RSOX, REOP, RVAL, RMOD,
and RERR
t7
Delay from RSCLK (Notes 1, 3)
2
9.5
ns
TDATA, TPRTY, TADR,
TEN,
TSOX, TEOP, TMOD, and
TERR
t5
Hold time from TSCLK (Note 1)
0
ns
TDATA, TPRTY, TADR,
TEN,
TSOX, TEOP, TMOD, and
TERR
t6
Setup time to TSCLK (Note 1)
3.5
ns
TPXA and TSPA
t7
Delay from TSCLK (Notes 1, 3)
2
9.5
ns
Note 1:
The input/output timing reference level for all signals is VDD/2.
Note 2:
Rise and fall times are measured at output side with the output unloaded. Rise time is measured from 20% to 80% VOH. Fall time
is measured from 80% to 20% VOH.
Note 3:
These times are met with a 30pF, 300
load on the associated output pin.