參數(shù)資料
型號： DS3154N
英文描述： Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
中文描述： 單/雙/三/四DS3/E3/STS-1柳斯
文件頁數(shù)： 40/60頁
文件大?。?/td> 788K
代理商： DS3154N
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
40 of 60
Table 13-F. Transmitter Output Characteristics—DS3 and STS-1 Modes
(V
DD
= 3.3V 5%, T
A
= -40°C to +85°C.)
PARAMETER
DS3 Output Pulse Amplitude, TLBO = 0 (Note 17)
DS3 Output Pulse Amplitude, TLBO = 1 (Note 17)
STS-1 Output Pulse Amplitude, TLBO = 0 (Note 17)
STS-1 Output Pulse Amplitude, TLBO = 1 (Note 17)
Ratio of Positive and Negative Pulse-Peak Amplitudes
DS3 Unframed All-Ones Power Level at 22.368MHz, 3kHz Bandwidth
DS3 Unframed All-Ones Power Level at 44.736MHz vs. Power Level at
22.368MHz, 3kHz Bandwidth
Intrinsic Jitter Generation (Note 18)
Table 13-G. Transmitter Output Characteristics—E3 Mode
(V
DD
= 3.3V 5%, T
A
= -40°C to +85°C.)
PARAMETER
Output Pulse Amplitude (Note 17)
Pulse Width
Ratio of Positive and Negative Pulse Amplitudes (at Centers of Pulses)
Ratio of Positive and Negative Pulse Widths (at Nominal Half Amplitude)
Intrinsic Jitter Generation (Note 18)
Note 17:
Measured on the line side (i.e., the BNC connector side) of the 2:1 transmit transformer (
Figure 1-1
).
Note 18:
Measured with jitter-free clock applied to TCLK and a bandpass jitter filter with 10Hz and 800kHz cutoff frequencies. Not tested during
production test.
Table 13-H. CPU Bus Timing
(
V
DD
= 3.3V 5%, T
A
= -40°C to +85°C.
) (
Figure 13-3
and
Figure 13-4
)
PARAMETER
Setup Time for A[5:0] Valid to
CS
Active (Notes 19, 20)
Setup Time for
CS
Active to
RD
,
WR
, or
DS
Active
Delay Time from
RD
or
DS
Active to D[7:0] Valid
Hold Time from
RD
or
WR
or
DS
Inactive to
CS
Inactive
Delay from
CS
or
RD
or
DS
Inactive to D[7:0] Invalid or Tri-State
(Note 21)
Wait Time from
WR
or
DS
Active to Latch D[7:0]
D[7:0] Setup Time to
WR
or
DS
Inactive
D[7:0] Hold Time from
WR
or
DS
Inactive
A[5:0] Hold Time from
WR
or
RD
or
DS
Inactive
RD
,
WR
, or
DS
Inactive Time
Muxed Address Valid to ALE Falling (Note 22)
Muxed Address Hold Time (Note 22)
ALE Pulse Width (Note 22)
Setup Time for ALE High or Muxed Address Valid to
CS
Active
(Note 22)
Note 19:
D[7:0] loaded with 50pF when tested as outputs.
Note 20:
If a gapped clock is applied on TCLK and diagnostic loopback is enabled, read cycle time must be extended by the length of the
largest TCLK gap.
Note 21:
Not tested during production test.
Note 22:
In nonmultiplexed bus applications (
Figure 13-3
), ALE should be wired high. In multiplexed bus applications (
Figure 13-4
), A[5:0]
should be wired to D[5:0] and the falling edge of ALE latches the address.
MIN
700
520
700
520
0.9
-1.8
TYP
800
700
800
700
MAX
900
800
1100
850
1.1
+5.7
UNITS
mVpk
mVpk
mVpk
mVpk
dBm
-20
dB
0.02
0.05
UI
P-P
MIN
900
0.95
0.95
TYP
1000
14.55
0.02
MAX
1100
1.05
1.05
0.05
UNITS
mVpk
ns
UI
P-P
SYMBOL
t1
t2
t3
t4
MIN
0
0
0
TYP
MAX
65
UNITS
ns
ns
ns
ns
t5
2
20
ns
t6
t7
t8
t9
t10
t11
t12
t13
65
10
2
5
75
10
10
30
ns
ns
ns
ns
ns
ns
ns
ns
t14
0
ns
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