參數(shù)資料
型號(hào)： DS3154N
英文描述： Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
中文描述： 單/雙/三/四DS3/E3/STS-1柳斯
文件頁(yè)數(shù)： 12/60頁(yè)
文件大?。?/td> 788K
代理商： DS3154N
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
12 of 60
Table 4-C. Receiver Pin Descriptions
NAME
RXPn,
RXNn
I/O
FUNCTION
I
Receiver Analog Inputs. These differential AMI inputs are coupled to the inbound 75 coaxial cable
through a 1:2 step-up transformer (
Figure 1-1
).
Receiver Clock. The recovered clock is output on the RCLK pin. Recovered data is output on the
RPOS/RDAT and RNEG/RLCV pins on the falling edge of RCLK (RCINV = 0) or the rising edge of
RCLK (RCINV = 1). During a loss of signal (
RLOS
= 0), the RCLK output signal is derived from the
LIU’s master clock.
Receiver Positive AMI/Receiver Data. When the receiver is configured to have a bipolar interface
(RBIN = 0), RPOS pulses high for each positive AMI pulse received. When the receiver is
configured to have a binary interface (RBIN = 1), RDAT outputs decoded binary data. RPOS/RDAT
is updated either on the falling edge of RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).
Receiver Negative AMI/Line-Code Violation. When the receiver is configured to have a bipolar
interface (RBIN = 0), RNEG pulses high for each negative AMI pulse received. When the receiver is
configured to have a binary interface (RBIN = 1), RLCV pulses high to flag code violations. See
Section
6
for further details on code violations. RNEG/RLCV is updated either on the falling edge of
RCLK (RCINV = 0) or the rising edge of RCLK (RCINV = 1).
Receiver Tri-State Enable (Active Low).
RTS
tri-states the RPOS/RDAT, RNEG/RLCV, and RCLK
receiver outputs. This feature supports applications requiring LIU redundancy. Receiver outputs
from multiple LIUs can be wire-ORed together, eliminating the need for external switches or muxes.
The receiver continues to operate internally when
RTS
is low.
0 = tri-state the receiver outputs
1 = enable the receiver outputs
Receiver Loss of Signal (Active Low, Open Drain).
RLOS
is asserted upon detection of 175 75
consecutive zeros in the receive data stream.
RLOS
is deasserted when there are no excessive
zero occurrences over a span of 175 75 clock periods. An excessive zero occurrence is defined as
three or more consecutive zeros in the DS3 and STS-1 modes or four or more zeros in the E3
mode. See Section
6
for additional details.
Receive Monitor-Preamp Enable. RMON determines whether or not the receiver’s preamp is
enabled to provide flat gain to the incoming signal before the AGC/equalizer block processes it. This
feature should be enabled when the device is being used to monitor signals that have been
resistively attenuated by a monitor jack.
0 = disable the monitor preamp
1 = enable the monitor preamp
Receiver Jitter Attenuator Enable
0 = remove jitter attenuator from the receiver path
1 = insert jitter attenuator into the receiver path
(Note that TJA = 1 takes precedence over RJA = 1.)
RCLKn
O3
RPOSn/
RDATn
O3
RNEGn/
RLCVn
O3
RTSn
I
RLOSn
O
RMONn
I
RJAn
I
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3154N# 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3154N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3154NA2 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3154NB1 制造商:Maxim Integrated Products 功能描述:DS3154B QUAD DS3/E3 LIU IND - Rail/Tube 制造商:Maxim Integrated Products 功能描述:DS3/E3/STS-1 LIUS
DS3154NCA2 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
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