參數(shù)資料
型號: DS3112N
廠商: Maxim Integrated Products
文件頁數(shù): 86/133頁
文件大?。?/td> 0K
描述: IC MUX TEMPE T3/E3 IND 256-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: 調(diào)幀器,多路復(fù)用器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 150mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-PBGA(27x27)
包裝: 管件
DS3112
56 of 133
Table 5-1. T3 Alarm Criteria
ALARM/
CONDITION
DEFINITION
SET CRITERIA
CLEAR CRITERIA
AIS
Alarm Indication Signal
Properly framed 1010...
pattern, which is aligned
with the 1 just after each
overhead bit and all C bits
are set to zero
In each 84-bit information
field, the properly aligned
10... pattern is detected with
less than 4-bit errors (out of
84 possible) for 1024
consecutive information bit
fields (1.95ms) and all C bits
are majority decoded to be
zero during this time
In each 84 bit information
field, the properly aligned
10... pattern is detected with
4 or more bit errors (out of 84
possible) for 1024
consecutive information bit
fields (1.95ms)
LOS
Loss Of Signal
(Note 2)
192 consecutive zeros
No EXZ events over a 192-
bit window that starts with
the first one received
LOF
Loss Of Frame
Too many F bits or M bits in
error
Three or more F bits in error
out of 16 consecutive, or 2 or
more M bits in error out of
four consecutive
Synchronization occurs
RAI
(Note 1)
Remote Alarm Indication
(This is also referred to as
SEF/AIS in Bellcore GR-
820)
Inactive: X1 = X2 = 1
Active: X1 = X2 = 0
X1 and X2 = 0 for four
consecutive M frames (426s)
X1 and X2 = 1 for four
consecutive M frames
(426s)
Idle Signal
Properly framed 1100...
pattern, which is aligned
with the 11 just after each
overhead bit and the C bits
in Subframe 3 are zero.
In each 84-bit information
field, the properly aligned
1100... pattern is detected with
less than 4-bit errors (out of
84 possible) for 1024
consecutive information bit
fields (1.95ms) and the C bits
in Subframe 3 are majority
decoded to be zero during this
time.
In each 84-bit information
field, the properly aligned
1100... pattern is detected
with four or more bit errors
(out of 84 possible) for 1024
consecutive information bit
fields (1.95ms)
Note 1: RAI can also be indicated via FEAC codes in the C-Bit Parity Mode
Note 2: LOS is not defined for unipolar (binary) operation.
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