參數(shù)資料
型號: DS3112N+
廠商: Maxim Integrated Products
文件頁數(shù): 129/133頁
文件大?。?/td> 0K
描述: IC MUX TEMPE T3/E3 256-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: 調(diào)幀器,多路復(fù)用器
接口: 并行/串行
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 150mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-PBGA(27x27)
包裝: 管件
DS3112
95 of 133
Register Name:
IHSR
Register Description:
Interrupt Mask for HDLC Status Register
Register Address:
88h
Bit #
7
6
5
4
3
2
1
0
Name
TUDR
RPE
RPS
RHWM
TLWM
TEND
Default
0
0
0
Bit #
15
14
13
12
11
10
9
8
Name
RABT
ROVR
Default
0
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: Transmit Packet End (TEND).
0 = interrupt masked
1 = interrupt unmasked
Bit 2: Transmit FIFO Low Watermark (TLWM).
0 = interrupt masked
1 = interrupt unmasked
Bit 4: Receive FIFO High Watermark (RHWM).
0 = interrupt masked
Bit 13: Receive FIFO Overrun (ROVR).
1 = interrupt unmasked
Bit 5: Receive Packet Start (RPS).
0 = interrupt masked
1 = interrupt unmasked
Bit 6: Receive Packet End (RPE).
0 = interrupt masked
1 = interrupt unmasked
Bit 7: Transmit FIFO Underrun (TUDR).
0 = interrupt masked
1 = interrupt unmasked
0 = interrupt masked
1 = interrupt unmasked
Bit 15: Receive Abort Sequence Detected (RABT).
0 = interrupt masked
1 = interrupt unmasked
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DS3112 IC MUX TEMPE T3/E3 256-BGA
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