參數(shù)資料
型號: DS26504L+
廠商: Maxim Integrated Products
文件頁數(shù): 58/129頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
功能: BITS 元件
接口: 64KCC,E1,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 150mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
包括: *
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26504 T1/E1/J1/64KCC BITS Element
34 of 129
7.3.1 Power-Up Sequence
The DS26504 contains an on-chip power-up reset function that automatically clears the writeable register
space immediately after power is supplied to the device. The user can issue a chip reset at any time.
Issuing a reset will disrupt signals flowing through the DS26504 until the device is reprogrammed. The
reset can be issued through hardware using the TSTRST pin or through software using the SFTRST
function in the master mode register. The LIRST (LIC2.6) should be toggled from zero to one to reset the
line interface circuitry. (It will take the DS26504 about 40ms to recover from the LIRST bit being
toggled.)
7.3.2 Test Reset Register
Register Name:
TSTRREG
Register Description:
Test Reset Register
Register Address:
00h
Bit #
7
6
5
4
3
2
1
0
Name
TEST1
TEST0
SFTRST
Default
0
HW
Mode
X
Bit 0: Software-Issued Reset (SFTRST). A zero-to-one transition causes the register space in the DS26504 to be cleared. A
reset clears all configuration and status registers. The bit automatically clears itself when the reset has completed.
Bits 1, 2, 3, 6, 7: Unused, must be set = 0 for proper operation.
Bits 4 and 5: Test Mode Bits (TEST0 and TEST1). Test modes are used to force the output pins of the DS26504 into known
states. This can facilitate the checkout of assemblies during the manufacturing process and also be used to isolate devices from
shared buses.
TEST1
TEST0
EFFECT ON OUTPUT PINS
0
Operate normally
0
1
Force all output pins into three-state (including all I/O pins and parallel port pins)
1
0
Force all output pins low (including all I/O pins except parallel port pins)
1
Force all output pins high (including all I/O pins except parallel port pins)
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