參數(shù)資料
型號: DS26504L+
廠商: Maxim Integrated Products
文件頁數(shù): 111/129頁
文件大?。?/td> 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
功能: BITS 元件
接口: 64KCC,E1,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 150mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
包括: *
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS26504 T1/E1/J1/64KCC BITS Element
82 of 129
13.2.2 Receive G.703 Section 13 Synchronization Signal
The DS26504 can receive a 2.048MHz square-wave synchronization clock as specified in Section 13 of
ITU G.703. To use the DS26504 in this mode, set the mode configuration bits in the Mode Configuration
Register (MCREG).
13.2.3 Monitor Mode
Monitor applications in both E1 and T1 require various flat-gain settings for the receive-side circuitry.
The DS26504 can be programmed to support these applications via the monitor mode control bits MM1
and MM0 in the LIC3 register.
Figure 13-2. Typical Monitor Application
PRIMARY
T1/E1 TERMINATING
DEVICE
MONITOR
PORT JACK
T1/E1 LINE
X
F
M
R
DS26504
Rt
Rm
SECONDARY T1/E1
TERMINATING
DEVICE
13.3 LIU Transmitter
The DS26504 uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create
the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the DS26504 meet
the latest ETSI, ITU, ANSI, and AT&T specifications. The waveform that is to be generated is set by the
transmit mode bits (TMODE[3:0]) in the MCREG register, as well as the L2/L1/L0 bits in register LIC1
if applicable.
ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs
require an accuracy of ±32ppm for T1 interfaces. The transmit clock can be sourced from the recovered
clock (RCLK), the pre-scaled MCLK, the TCLK pin, or the TX PLL. See the TX PLL clock mux
diagram in Figure 3-3. Due to the nature of the design of the transmitter in the DS26504, very little jitter
(less than 0.005UIP-P broadband from 10Hz to 100kHz) is added to the jitter present on the selected
transmit clock source. Also, the waveforms created are independent of the duty cycle of TCLK. The
transmitter in the DS26504 couples to the transmit twisted pair (or coaxial cable in some applications) via
a 1:2 step-up transformer. For the device to create the proper waveforms, the transformer used must meet
the specifications listed in Table 13-3. The DS26504 has the option of using software-selectable transmit
termination.
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