參數(shù)資料
型號(hào): DS2482S-100+T&R
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 11/24頁(yè)
文件大?。?/td> 0K
描述: IC I2C TO 1WIRE BRIDGE 8SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
其它名稱: DS2482S-100+T&RDKR
Single-Channel 1-Wire Master
1-Wire Single Bit (To Generate a Single Time Slot on the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the
result from the 1-Wire Single Bit command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed
When 1WB has changed from 1 to 0, the Status Register holds the valid result of the 1-Wire Single Bit command.
Case C: 1-Wire Busy (1WB = 1)
The master should stop and restart as soon as the DS2482-100 does not acknowledge the command code.
1-Wire Write Byte (To Send a Command Code to the 1-Wire Line)
Case A: 1-Wire Idle (1WB = 0), No Busy Polling
33h is the valid 1-Wire ROM function command for Read ROM. The idle time is needed for the 1-Wire function to
complete. There is no data read back from the 1-Wire line with this command.
Case B: 1-Wire Idle (1WB = 0), Busy Polling Until the 1-Wire Command is Completed.
When 1WB has changed from 1 to 0, the 1-Wire Write Byte command is completed.
Case C: 1-Wire Busy (1WB = 1)
The master should stop and restart as soon as the DS2482-100 does not acknowledge the command code.
S
AD,0
A
1WWB
A\
P
S
AD,0
A
1WWB
A
33h
A
AD,1
Sr
AA
<byte>
A\
P
REPEAT UNTIL THE 1WB BIT
HAS CHANGED TO 0.
S
AD,0
A
1WWB
A
33h
A
P
(Idle)
S
AD,0
A
1WSB
A\
P
S
AD,0
A
1WSB
A
<byte>
Sr
AD,1
AA
<byte>
A\
P
REPEAT UNTIL THE 1WB BIT
HAS CHANGED TO 0.
S
AD,0
A
1WSB
A
<byte>
P
(Idle)
S
AD,1
A
<byte>
A\
P
I2C Communication Examples (continued)
DS2482-100
Maxim Integrated
19
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