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參數(shù)資料
| 型號： | DS2423 |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4kbit 1-Wire RAM with Counter |
| 中文描述： | 4k位1-Wire RAM，帶有計數(shù)器 |
| 文件頁數(shù)： | 25/25頁 |
| 文件大?。?/td> | 331K |
| 代理商： | DS2423 |
DS2423
25 of 25
NOTES:
1)
All voltages are referenced to ground.
2)
V
PUP
= external pullup voltage.
3)
Input load is to ground.
4)
An additional reset or communication sequence cannot begin until the reset high time has expired.
5)
Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is
guaranteed to be valid within 1μs of this falling edge.
6)
Capacitance on the data pin could be 800pF when power is first applied. If a 5k
resistor is used to
pull up the data line to V
PUP
, 5μs after power has been applied the parasite capacitance will not affect
normal communications.
7)
The reset low time (t
RSTL
) should be restricted to a maximum of 960μs, to allow interrupt signaling,
otherwise, it could mask or conceal interrupt pulses.
8)
V
IH
is a function of the external pullup resistor and V
PUP
.
9)
Under certain low voltage conditions V
ILMAX
may have to be reduced to as much as 0.5V to always
guarantee a Presence Pulse.
10)
The counter inputs are designed for interfacing to mechanical switches and piezo sensors. If
interfacing to digital circuits, one should use an open drain driver.
11)
A lower impedance pullup, e. g., for reed switches, can be achieved by connecting an external resistor
from the counter input to V
BAT
.
12)
Read and write scratchpad (all 32 bytes) at V
BAT
of 3.0 V.
13)
Each low-going edge on a counter input resets the channel’s debounce timer. The debounce time
starts as the input voltage rises beyond the trip point. In order for the next pulse to be counted the
debounce time must have expired.
14)
The optimal sampling point for the master is as close as possible to the end time of the t
RDV
period
without exceeding t
RDV
. For the case of a Read-One Time slot, this maximizes the amount of time for
the pullup resistor to recover to a high level. For a Read-Zero Time slot, it ensures that a read will
occur before the fastest 1-Wire device(s) releases the line.
15)
The duration of the low pulse sent by the master should be a minimum of 1
μ
s with a maximum value
as short as possible to allow time for the pullup resistor to recover the line to a high level before the 1-
Wire device samples in the case of a Write-One Time or before the master samples in the case of a
Read-One Time.
16)
Guaranteed by design; not production tested.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS2423P | 4kbit 1-Wire RAM with Counter |
| DS2423X | 4kbit 1-Wire RAM with Counter |
| DS2430A | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| DS2430AP | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2423D/T&R | 制造商:Maxim Integrated Products 功能描述:IC SRAM 4KBIT 6FLIPCHIP |
| DS2423D/T&R | 功能描述:IC SRAM 4KBIT 6FCHIP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:150 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 線串口 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-VFDFN 裸露焊盤 供應商設(shè)備封裝:8-DFN（2x3） 包裝:管件 產(chǎn)品目錄頁面:1445 (CN2011-ZH PDF) |
| DS2423MRAB0 | 制造商:Thomas & Betts 功能描述:300A,NLT,3P4W,MG,423,3P480V |
| DS2423P | 功能描述:靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| DS2423P/R | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:4kbit 1-Wire RAM with Counter |
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