參數(shù)資料
型號(hào): DS2423
元件分類: 通用總線功能
英文描述: 4kbit 1-Wire RAM with Counter
中文描述: 4k位1-Wire RAM,帶有計(jì)數(shù)器
文件頁(yè)數(shù): 21/25頁(yè)
文件大?。?/td> 331K
代理商: DS2423
DS2423
21 of 25
Read-Data Time Slot
RESISTOR
MASTER
DS2423
t
REC
V
PUP
V
PUPMIN
V
IHMIN
V
ILMAX
0V
Master
Sampling
Window
t
LOWR
t
SLOT
t
SU
t
RDV
t
RELEASE
CRC GENERATION
With the DS2423 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-
bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC
value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS2423 to
determine if the ROM data has been received error-free by the bus master. The equivalent polynomial
function of this CRC is: X
8
+ X
5
+ X
4
+ 1. This 8-bit CRC is received in the true (non-inverted) form
when reading the ROM of the DS2423. It is computed at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function x
16
+ x
15
+ x
2
+ 1. This CRC is used for error detection when reading Data Memory using the Read Memory
+ Counter command and for fast verification of a data transfer when writing to the scratchpad. It is the
same type of CRC as is used with NV RAM based iButtons for error detection within the iButton
Extended File Structure. In contrast to the 8-bit CRC, the 16-bit CRC is always returned or sent in the
complemented (inverted) form. A CRC-generator inside the DS2423 chip (Figure 12) will calculate a new
16-bit CRC as shown in the command flow chart of Figure 7. The bus master compares the CRC value
read from the device to the one it calculates from the data and decides whether to continue with an
operation or re-read the portion of the data with the CRC error.
With the initial pass through the Read Memory + Counter flow chart the 16-bit CRC value is the result of
shifting the command byte into the cleared CRC generator, followed by the two address bytes, data bytes,
value of the counter associated with the page and zero bits. Subsequent passes through the Read Memory
+ Counter flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then
shifting in the data bytes, the value of the counter and the zero bits.
With the Write Scratchpad command the CRC is generated by first clearing the CRC generator and then
shifting in the command code, the Target Addresses TA1 and TA2 and all the data bytes. The DS2423
will transmit this CRC only if the data bytes written to the scratchpad include scratchpad ending offset
11111b. The data may start at any location within the scratchpad.
For more details on generating CRC values including example implementations in both hardware and
software, see the
Book of DS19xx iButton Standards
.
相關(guān)PDF資料
PDF描述
DS2423P 4kbit 1-Wire RAM with Counter
DS2423X 4kbit 1-Wire RAM with Counter
DS2430A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
DS2430 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
DS2430AP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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