參數(shù)資料
型號(hào)： DS2423
元件分類： 通用總線功能
英文描述： 4kbit 1-Wire RAM with Counter
中文描述： 4k位1-Wire RAM，帶有計(jì)數(shù)器
文件頁(yè)數(shù)： 19/25頁(yè)
文件大小： 331K
代理商： DS2423
DS2423
19 of 25
1-WIRE SIGNALING
The DS2423 requires strict protocols to ensure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read
Data. The bus master initiates all these signals except Presence Pulse. The DS2423 can communicate at
two different speeds, regular speed and Overdrive speed. If not explicitly set into the Overdrive mode, the
DS2423 will communicate at regular speed. While in Overdrive mode the fast timing applies to all
waveforms.
The initialization sequence required to begin any communication with the DS2423 is shown in Figure 10.
A Reset Pulse followed by a Presence Pulse indicates the DS2423 is ready to send or receive data given
the correct ROM command and memory function command. The bus master transmits (TX) a Reset
Pulse (t
RSTL
, minimum 480 μs at regular speed, 48 μs at Overdrive speed). The bus master then releases
the line and goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor.
After detecting the rising edge on the data pin, the DS2423 waits (t
PDH
, 15-60μs at regular speed, 2-6μs at
Overdrive speed) and then transmits the Presence Pulse (t
PDL
, 60-240μs at regular speed, 8-24μs at
Overdrive speed).
A Reset Pulse of 480μs or longer will exit the Overdrive mode returning the device to regular speed. If
the DS2423 is in Overdrive mode and the Reset Pulse is no longer than 80μs the device will remain in
Overdrive mode.
Read/Write Time Slots
The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the
master driving the data line low. The falling edge of the data line synchronizes the DS2423 to the master
by triggering a delay circuit in the DS2423. During write time slots, the delay circuit determines when the
DS2423 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2423 will hold the data line low overriding the 1 generated by the master. If
the data bit is a “1”, the device will leave the read data time slot unchanged.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES”
Figure 10
DS2423
相關(guān)PDF資料
PDF描述
DS2423P 4kbit 1-Wire RAM with Counter
DS2423X 4kbit 1-Wire RAM with Counter
DS2430A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
DS2430 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
DS2430AP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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DS2423P 功能描述:靜態(tài)隨機(jī)存取存儲(chǔ)器 RoHS:否 制造商:Cypress Semiconductor 存儲(chǔ)容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
DS2423P/R 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:4kbit 1-Wire RAM with Counter
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