參數(shù)資料
型號(hào): DS2423
元件分類: 通用總線功能
英文描述: 4kbit 1-Wire RAM with Counter
中文描述: 4k位1-Wire RAM,帶有計(jì)數(shù)器
文件頁數(shù): 14/25頁
文件大?。?/td> 331K
代理商: DS2423
DS2423
14 of 25
HARDWARE CONFIGURATION
Figure 8
Note: Depending on the 1-Wire communication speed and the bus load characteristics, the optimal pull-
up resistor (R
PU
) value will be in the 1.5k to 5k range.
1-WIRE BUS SYSTEM
The 1-Wire bus is a system which has a single bus master and one or more slaves. In all instances the
DS2423 is a slave device. The bus master is typically a microcontroller. The discussion of this bus
system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire
signaling (signal types and timing). A 1-Wire protocol defines bus transactions in terms of the bus state
during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a
more detailed protocol description, refer to Chapter 4 of the
Book of DS19xx iButton Standards
.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to
drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-
drain or 3-state outputs. The 1-Wire port of the DS2423 is open drain with an internal circuit equivalent
to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At
regular speed the 1-Wire bus has a maximum data rate of 16.3kbits per second. The speed can be boosted
to 142kbits per second by activating the Overdrive mode. The 1-Wire bus requires a pullup resistor of
approximately 5k
. The 1-Wire bus requires a pullup resistor range of 1.5k to 5k , depending on the
bus load characteristics.
The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus
MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low
for more than 16μs (Overdrive speed) or more than 120μs (regular speed), one or more devices on the bus
may be reset.
TRANSACTION SEQUENCE
The protocol for accessing the DS2423 via the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory Function Command
Transaction/Data
R
PU
DS2423
相關(guān)PDF資料
PDF描述
DS2423P 4kbit 1-Wire RAM with Counter
DS2423X 4kbit 1-Wire RAM with Counter
DS2430A The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
DS2430 The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
DS2430AP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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