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參數(shù)資料
| 型號： | DS2408S+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 34/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH 8-CHAN ADDRESS 16SOIC |
| 標準包裝： | 2,500 |
| 接口： | 1 線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | * |
| 電源電壓： | 2.8 V ~ 5.25 V |
| 工作溫度： | * |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
| 包括： | * |
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DS2408
4 of 39
Note 1:
System Requirement
Note 2:
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the
system and 1-Wire recovery times. The specified value here applies to systems with only one
device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an
active pullup such as that found in the DS2480B may be required.
Note 3:
If a 2.2k resistor is used to pull up the data line to VPUP, 5s after power has been applied,
the parasite capacitance does not affect normal communications.
Note 4:
Guaranteed by design—not production tested.
Note 5:
VTL and VTH are functions of the internal supply voltage, which in parasitic power mode, is a
function of VPUP and the 1-Wire recovery times. The VTH and VTL maximum specifications
are valid at VPUP = 5.25V. In any case, VTL < VTH < VPUP.
Note 6:
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
Note 7:
The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line
low.
Note 8:
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
Note 9:
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be
detected as logic '0'.
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: The earliest recognition of a negative edge is possible at tREH after VTH has been reached
before.
Note 12: Highlighted numbers are NOT in compliance with the published 1-Wire standards. See
comparison table below.
Note 13: Interval during the negative edge on I/O at the beginning of a presence detect pulse between
the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of
VPUP.
Note 14: ε in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
up from VIL to VTH. The actual maximum duration for the master to pull the line low is
tW1LMAX + tF - ε and tW0LMAX + tF - ε respectively.
Note 15: δ in Figure 14 represents the time required for the pullup circuitry to pull the voltage on I/O
up from VIL to the input high threshold of the bus master. The actual maximum duration for
the master to pull the line low is tRLMAX + tF.
Note 16: Interval during the device-generated negative edge on any PIO pin or the RSTZ pin between
the time at which the voltage is 90% of VPUP and the time at which the voltage is 10% of
VPUP. PIO pullup resistor = 2.2k.
Note 17: Width of the narrowest pulse which trips the activity latch (for any PIO pin) or causes a reset
(for the RSTZ pin). For a pulse duration tPW: If tPW < tPWMIN(min), the pulse will be rejected. If
tPWMIN(min) < tPW < tPWMIN(max), the pulse may or may not be rejected. If tPW > tPWMIN(max) the
pulse will be recognized and latched.
Note 18: Maximum instantaneous pulldown current through all port pins and the RSTZ pin combined.
No requirement for current balance among different pins.
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