參數(shù)資料
型號(hào)： DS2408S+T&R
廠(chǎng)商： Maxim Integrated Products
文件頁(yè)數(shù)： 19/39頁(yè)
文件大?。?/td> 0K
描述： IC SWITCH 8-CHAN ADDRESS 16SOIC
標(biāo)準(zhǔn)包裝： 2,500
接口： 1 線(xiàn)
輸入/輸出數(shù)： 8
中斷輸出： *
電源電壓： 2.8 V ~ 5.25 V
工作溫度： *
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC
包裝： 帶卷 (TR)
包括： *
DS2408
26 of 39
Read-Data Time Slot
Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below
VTLMIN until the read low time tRL has expired. During the tRL window, when responding with a 0, the
DS2408 starts pulling the data line low; its internal timing generator determines when this pulldown ends
and the voltage starts rising again. When responding with a 1, the DS2408 does not hold the data line low
at all, and the voltage starts rising as soon as tRL is over.
The sum of tRL + δ (rise time) on one side and the internal timing generator of the DS2408 on the other
side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read
from the data line. For most reliable communication, tRL should be as short as permissible and the master
should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until
tSLOT is expired. This guarantees sufficient recovery time tREC for the DS2408 to get ready for the next
time slot.
Improved Network Behavior
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks therefore are susceptible to noise of various origins. Depending on the
physical size and topology of the network, reflections from end points and branch points can add up or
cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire
communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal
glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization
with the master and, as a consequence, result in a Search ROM command coming to a dead end or cause a
device level command to abort. For better performance in network applications, the DS2408 uses a new
1-Wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected
by the slave device itself.
The 1-Wire front end of the DS2408 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the
line impedance than a digitally switched transistor, converting the high-frequency ringing known
from traditional devices into a smoother low-bandwidth transition. The slew rate control is specified
by the parameter tFPD, which has different values for standard and overdrive speed.
2) There is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a
time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply
at overdrive speed.
相關(guān)PDF資料
PDF描述
DS2409P/T&R IC COUPLER MICROLAN 1-WIRE 6TSOC
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DS2480B+ IC LINE DRVR W/SENSOR 1-W 8-SOIC
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