參數(shù)資料
型號： DS21Q42TN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQFP128
封裝： TQFP-128
文件頁數(shù)： 67/119頁
文件大?。?/td> 1309K
代理商： DS21Q42TN
DS21Q42
51 of 119
RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex)
(MSB)
(LSB)
A(8)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
A(1)
RS1 (60)
A(16)
A(15)
A(14)
A(13)
A(12)
A(11)
A(10)
A(9)
RS2 (61)
A(24)
A(23)
A(22)
A(21)
A(20)
A(19)
A(18)
A(17)
RS3 (62)
B(8)
B(7)
B(6)
B(5)
B(4)
B(3)
B(2)
B(1)
RS4 (63)
B(16)
B(15)
B(14)
B(13)
B(12)
B(11)
B(10)
B(9)
RS5 (64)
B(24)
B(23)
B(22)
B(21)
B(20)
B(19)
B(18)
B(17)
RS6 (65)
A/C(8)
A/C(7)
A/C(6)
A/C(5)
A/C(4)
A/C(3)
A/C(2)
A/C(1)
RS7 (66)
A/C(16)
A/C(15)
A/C(14)
A/C(13)
A/C(12)
A/C(11)
A/C(10)
A/C(9)
RS8 (67)
A/C(24)
A/C(23)
A/C(22)
A/C(21)
A/C(20)
A/C(19)
A/C(18)
A/C(17) RS9 (68)
B/D(8)
B/D(7)
B/D(6)
B/D(5)
B/D(4)
B/D(3)
B/D(2)
B/D(1)
RS10 (69)
B/D(16)
B/D(15)
B/D(14)
B/D(13)
B/D(12)
B/D(11)
B/D(10)
B/D(9)
RS11 (6A)
B/D(24)
B/D(23)
B/D(22)
B/D(21)
B/D(20)
B/D(19)
B/D(18)
B/D(17)
RS12 (6B)
SYMBOL
POSITION
NAME AND DESCRIPTION
D(24)
RS12.7
Signaling Bit D in Channel 24
A(1)
RS1.0
Signaling Bit A in Channel 1
Each Receive Signaling Register (RS1 to RS12) reports the incoming robbed bit signaling from eight
DS0 channels. In the ESF framing mode, there can be up to four signaling bits per channel (A, B, C,
and D). In the D4 framing mode, there are only two signaling bits per channel (A and B). In the D4
framing mode, the framer will replace the C and D signaling bit positions with the A and B signaling bits
from the previous multiframe. Hence, whether the framer is operated in either framing mode, the user
needs only to retrieve the signaling bits every 3 ms. The bits in the Receive Signaling Registers are
updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive
Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The Receive Signaling Registers
are frozen and not updated during a loss of sync condition (SR1.0=1). They will contain the most recent
signaling information before the “OOF” occurred. The signaling data reported in RS1 to RS12 is also
available at the RSIG and RSER pins.
A change in the signaling bits from one multiframe to the next will cause the RSC status bit (SR2.0) to be
set. The user can enable the INT* pin to toggle low upon detection of a change in signaling by setting the
IMR2.0 bit. Once a signaling change has been detected, the user has at least 2.75 ms to read the data out
of the RS1 to RS12 registers before the data will be lost.
相關(guān)PDF資料
PDF描述
DS21Q42T DATACOM, FRAMER, PQFP128
DS21Q43AT DATACOM, FRAMER, PQFP128
DS21Q44T DATACOM, FRAMER, PQFP128
DS21Q44TN DATACOM, FRAMER, PQFP128
DS21Q48N DATACOM, PCM TRANSCEIVER, PBGA144
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DS21Q43-ATN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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