參數(shù)資料
型號(hào)： DS21Q42TN
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQFP128
封裝： TQFP-128
文件頁(yè)數(shù)： 63/119頁(yè)
文件大?。?/td> 1309K
代理商： DS21Q42TN
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DS21Q42
48 of 119
MULTIFRAMES OUT OF SYNC COUNTING ARRANGEMENTS Table 8-3
FRAMING
MODE
(CCR2.3)
COUNT MOS
OR F–BIT
ERRORS
(RCR2.0)
WHAT IS COUNTED IN THE MOSCRs
D4
MOS
number of multiframes out of sync
D4
F–Bit
errors in the Ft pattern
ESF
MOS
number of multiframes out of sync
ESF
F–Bit
errors in the FPS pattern
9. DS0 MONITORING FUNCTION
Each framer in the DS21Q42 has the ability to monitor one DS0 64 Kbps channel in the transmit
direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user
will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR5
register. In the receive direction, the RCM0 to RCM4 bits in the CCR6 register need to be properly set.
The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor
(TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive
DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the
decimal decode of the appropriate T1 channel. For example, if DS0 channel 6 (timeslot 5) in the transmit
direction and DS0 channel 15 (timeslot 14) in the receive direction needed to be monitored, then the
following values would be programmed into CCR5 and CCR6:
TCM4 = 0
RCM4 = 0
TCM3 = 0
RCM3 = 1
TCM2 = 1
RCM2 = 1
TCM1 = 0
RCM1 = 1
TCM0 = 1
RCM0 = 0
CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex)
[repeated here from section 6 for convenience]
(MSB)
(LSB)
TJC
–
TCM4
TCM3
TCM2
TCM1
TCM0
SYMBOL
POSITION
NAME AND DESCRIPTION
TJC
CCR5.7
Transmit Japanese CRC Enable. See Section 6 for details.
–
CCR5.5
Not Assigned. Must be set to zero when written.
–
CCR5.5
Not Assigned. Must be set to zero when written.
TCM4
CCR5.4
Transmit Channel Monitor Bit 4. MSB of a channel decode
that determines which transmit DS0 channel data will appear
in the TDS0M register.
TCM3
CCR5.3
Transmit Channel Monitor Bit 3.
TCM2
CCR5.2
Transmit Channel Monitor Bit 2.
TCM1
CCR5.1
Transmit Channel Monitor Bit 1.
TCM0
CCR5.0
Transmit Channel Monitor Bit 0. LSB of the channel decode
that determines which transmit DS0 channel data will appear
in the TDS0M register.
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