參數(shù)資料
型號: DS21Q42TN
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁數(shù): 30/119頁
文件大?。?/td> 1309K
代理商: DS21Q42TN
DS21Q42
18 of 119
Signal Name: RMSYNC
Signal Description: Receive Multiframe Sync
Signal Type: Output
An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If
the receive side elastic store is disabled, then this output will output multiframe boundaries associated
with RCLK. This function is available when FMS = 1 (DS21Q41 emulation).
Signal Name: RSYSCLK
Signal Description: Receive System Clock
Signal Type: Input
1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied low
in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz.
Signal Name: RSIG
Signal Description: Receive Signaling Output
Signal Type: Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
This function is available when FMS = 0.
Signal Name: RLOS/LOTC
Signal Description: Receive Loss of Sync / Loss of Transmit Clock
Signal Type: Output
A dual function output that is controlled by the CCR3.5 control bit. This pin can be programmed to either
toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5 usec. This function is available when FMS = 1 (DS21Q41
emulation).
Signal Name: CLKSI
Signal Description: 8 MHz Clock Reference
Signal Type: Input
A 1.544 MHz reference clock used in the generation of 8MCLK. This function is available when
FMS = 0.
Signal Name: 8MCLK
Signal Description: 8 MHz Clock
Signal Type: Output
A 8.192 MHz output clock that is referenced to the clock that is input at the CLKSI pin. This function is
available when FMS = 0.
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