參數(shù)資料
型號(hào): DS21Q42T
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁數(shù): 48/119頁
文件大小: 1309K
代理商: DS21Q42T
DS21Q42
34 of 119
SYMBOL
POSITION
NAME AND DESCRIPTION
TESMDM
CCR3.0
Transmit Elastic Store Minimum Delay Mode. See Section 13
for details.
0 = elastic stores operate at full two frame depth
1 = elastic stores operate at 32–bit depth
Pulse Density Enforcer
The Framer always examines both the transmit and receive data streams for violations of the following
rules which are required by ANSI T1.403:
no more than 15 consecutive zeros
at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23
Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits
respectively. When the CCR3.3 is set to one, the DS21Q42 will force the transmitted stream to meet this
requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should
be set to zero since B8ZS encoded data streams cannot violate the pulse density requirements.
CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex)
(MSB)
(LSB)
RSRE
RPCSI
RFSA1
RFE
RFF
THSE
TPCSI
TIRFS
SYMBOL
POSITION
NAME AND DESCRIPTION
RSRE
CCR4.7
Receive Side Signaling Re–Insertion Enable. See Section 10 for
details.
0 = do not re–insert signaling bits into the data stream presented at
the RSER pin
1 = reinsert the signaling bits into data stream presented at the
RSER pin
RPCSI
CCR4.6
Receive Per–Channel Signaling Insert. See Section 10 for more
details.
0 = do not use RCHBLK to determine which channels should have
signaling re–inserted
1 = use RCHBLK to determine which channels should have
signaling re–inserted
RFSA1
CCR4.5
Receive Force Signaling All Ones. See Section 10 for more
details.
0 = do not force extracted robbed–bit signaling bit positions to a one
1 = force extracted robbed–bit signaling bit positions to a one
RFE
CCR4.4
Receive Freeze Enable. See Section 10 for details.
0 = no freezing of receive signaling data will occur
1 = allow freezing of receive signaling data at RSIG (and RSER if
CCR4.7 = 1).
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DS21Q43AT DATACOM, FRAMER, PQFP128
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