參數(shù)資料
型號: DS21Q42T
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PQFP128
封裝: TQFP-128
文件頁數(shù): 33/119頁
文件大?。?/td> 1309K
代理商: DS21Q42T
DS21Q42
20 of 119
Signal Name: ALE(AS)/A6
Signal Description: A6 or Address Latch Enable (Address Strobe)
Signal Type: Input
In non–multiplexed bus operation (MUX = 0), serves as address bit 6. In multiplexed bus operation
(MUX = 1), serves to demultiplex the bus on a positive–going edge.
Signal Name: BTS
Signal Description: Bus Type Select
Signal Type: Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Signal Name: RD*(DS*)
Signal Description: Read Input (Data Strobe)
Signal Type: Input
RD* and DS* are active low signals. Note: DS is active high when MUX=1. Refer to bus timing
diagrams in section 21 .
Signal Name: FS0 AND FS1
Signal Description: Framer Selects
Signal Type: Input
Selects which of the four framers to be accessed.
Signal Name: CS*
Signal Description: Chip Select
Signal Type: Input
Must be low to read or write to the device. CS* is an active low signal.
Signal Name: WR*( R/W*)
Signal Description: Write Input(Read/Write)
Signal Type: Input
WR* is an active low signal.
TEST ACCESS PORT PINS
Signal Name: TEST
Signal Description: 3–State Control
Signal Type: Input
Set high to 3–state all output and I/O pins (including the parallel control port) when FMS = 1 or when
FMS = 0 and JTRST* is tied low. Set low for normal operation. Ignored when FMS = 0 and JTRST* = 1.
Useful in board level testing.
相關(guān)PDF資料
PDF描述
DS21Q43AT DATACOM, FRAMER, PQFP128
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DS21Q48 DATACOM, PCM TRANSCEIVER, PBGA144
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