參數(shù)資料
型號： DS21Q42T
廠商： DALLAS SEMICONDUCTOR
元件分類： Digital Transmission Controller
英文描述： DATACOM, FRAMER, PQFP128
封裝： TQFP-128
文件頁數(shù)： 102/119頁
文件大?。?/td> 1309K
代理商： DS21Q42T
DS21Q42
83 of 119
Instruction Codes For The DS21352/552 IEEE 1149.1 Architecture Table 19-1
Instruction
Selected Register
Instruction Codes
SAMPLE/PRELOAD
Boundary Scan
010
BYPASS
Bypass
111
EXTEST
Boundary Scan
000
CLAMP
Boundary Scan
011
HIGHZ
Boundary Scan
100
IDCODE
Device Identification
001
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS21Q42 can be sampled at the boundary scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS21Q42 to shift data into the boundary scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS21Q42. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The boundary scan register will be connected between
JTDI and JTDO. The Capture-DR will sample all digital inputs into the boundary scan register.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the
device’s normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register’s parallel output. The ID code will always have a ‘1’ in the LSB position. The next
11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits
for the device and 4 bits for the version. See Table 19-2. Table 19-3 lists the device ID codes for the
DS21Q42 and DS21Q44 devices.
ID Code Structure Table 19-2
MSB
LSB
Contents
Version
(Contact Factory)
Device ID
(See Table 19-3)
JEDEC
“00010100001”
“1”
Length
4 bits
16bits
11bits
1bit
相關(guān)PDF資料
PDF描述
DS21Q43AT DATACOM, FRAMER, PQFP128
DS21Q44T DATACOM, FRAMER, PQFP128
DS21Q44TN DATACOM, FRAMER, PQFP128
DS21Q48N DATACOM, PCM TRANSCEIVER, PBGA144
DS21Q48 DATACOM, PCM TRANSCEIVER, PBGA144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21Q42T+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q42TN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced Quad T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q43A 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Quad E1 Framer
DS21Q43AT 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21Q43AT+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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