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參數(shù)資料
| 型號(hào)： | DS21FF42N |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA300 |
| 封裝： | 27 X 27 MM, BGA-300 |
| 文件頁(yè)數(shù)： | 91/115頁(yè) |
| 文件大小： | 534K |
| 代理商： | DS21FF42N |
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DS21FF42/DS21FT42
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will automatically look for 5 ones in a row, followed by a zero. If it finds such a pattern, it will
automatically remove the zero. If the zero destuffer sees six or more ones in a row followed by a zero,
the zero is not removed. The CCR2.0 bit should always be set to a one when the DS21Q42 is extracting
the FDL. More on how to use the DS21Q42 in FDL applications in this legacy support mode is covered
in a separate Application Note.
RFDL: RECEIVE FDL REGISTER (Address = 28 Hex)
(MSB)
(LSB)
RFDL7
RFDL6
RFDL5
RFDL4
RFDL3
RFDL2
RFDL1
RFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
RFDL7
RFDL.7
MSB of the Received FDL Code
RFDL0
RFDL.0
LSB of the Received FDL Code
The Receive FDL Register (RFDL) reports the incoming Facility Data Link (FDL) or the incoming Fs
bits. The LSB is received first.
RMTCH1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex)
RMTCH2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex)
(MSB)
(LSB)
RMFDL7
RMFDL6
RMFDL5
RMFDL4
RMFDL3
RMFDL2
RMFDL1
RMFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
RMFDL7
RMTCH1.7
RMTCH2.7
MSB of the FDL Match Code
RMFDL0
RMTCH1.0
RMTCH2.0
LSB of the FDL Match Code
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RMTCH1/RMTCH2), SR2.2 will be set to a one and the INT* will go active if enabled via IMR2.2.
19.2.3 Transmit Section
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream. After the full 8 bits has been shifted out, the framer will signal the host microcontroller
that the buffer is empty and that more data is needed by setting the SR2.3 bit to a one. The INT* will
also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new value. If the
TFDL is not updated, the old value in the TFDL will be transmitted once again. The framer also contains
a zero stuffer, which is controlled via the CCR2.4 bit.
In both ANSI T1.403 and TR54016,
communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no
more than 5 ones should be transmitted in a row so that the data does not resemble an opening or closing
flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically
look for 5 ones in a row. If it finds such a pattern, it will automatically insert a zero after the five ones.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DS21FT44N | DATACOM, FRAMER, PBGA300 |
| DS21FT44 | DATACOM, FRAMER, PBGA300 |
| DS21Q352 | DATACOM, PCM TRANSCEIVER, PBGA256 |
| DS21Q354 | DATACOM, PCM TRANSCEIVER, PBGA256 |
| DS21Q41BT | DATACOM, FRAMER, PQFP128 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS21FF42N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl T1/T1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF44 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4x4 16/4x3 12 Chnl E1/E1 Framer RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FF44N | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS21FT40 | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Four x Three 12 Channel E1 Framer |
| DS21FT40N | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
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