DS21FF42/DS21FT42
4 of 115
TABLE OF CONTENTS
FEATURES ................................................................................................................................ 1
1. MULTI-CHIP MODULE (MCM) DESCRIPTION................................................................... 1
2. MCM LEAD DESCRIPTION................................................................................................. 7
3. DS21FF42 (FOUR X FOUR) PCB LAND PATTERN......................................................... 14
4. DS21FT42 (FOUR X THREE) PCB LAND PATTERN....................................................... 15
5. DS21Q42 FEATURES ....................................................................................................... 16
6. DS21Q42 INTRODUCTION ............................................................................................... 16
7. DS21Q42 PIN FUNCTION DESCRIPTION........................................................................ 19
8. DS21Q42 REGISTER MAP ............................................................................................... 27
9. PARALLEL PORT ............................................................................................................. 31
10.
CONTROL, ID AND TEST REGISTERS......................................................................... 31
11.
STATUS AND INFORMATION REGISTERS.................................................................. 42
12.
ERROR COUNT REGISTERS ........................................................................................ 49
13.
DS0 MONITORING FUNCTION...................................................................................... 52
14.
SIGNALING OPERATION .............................................................................................. 55
14.1 PROCESSOR BASED SIGNALING............................................................................. 55
14.2 HARDWARE BASED SIGNALING............................................................................... 57
15.
PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK ................................ 58
15.1 TRANSMIT SIDE CODE GENERATION...................................................................... 58
15.1.1 Simple Idle Code Insertion and Per–Channel Loopback........................................ 58
15.1.2 Per–Channel Code Insertion .................................................................................. 59
15.2 RECEIVE SIDE CODE GENERATION ........................................................................ 60
15.2.1 Simple Code Insertion ............................................................................................ 60
15.2.2 Per–Channel Code Insertion .................................................................................. 61
16.
CLOCK BLOCKING REGISTERS .................................................................................. 62