參數(shù)資料
型號(hào): DS21FF42N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, BGA-300
文件頁數(shù): 84/115頁
文件大?。?/td> 534K
代理商: DS21FF42N
DS21FF42/DS21FT42
70 of 115
SYMBOL
POSITION
NAME AND DESCRIPTION
RNE
HSR.3
Receive FIFO Not Empty. Set when the receive 64-byte
FIFO has at least one byte available for a read. The setting of
this bit prompts the user to read the RHIR register for details.
THALF
HSR.2
Transmit FIFO Half Empty. Set when the transmit 64 byte
FIFO empties beyond the half way point. The setting of this
bit prompts the user to read the THIR register for details.
TNF
HSR.1
Transmit FIFO Not Full. Set when the transmit 64-byte
FIFO has at least one byte available. The setting of this bit
prompts the user to read the THIR register for details.
TMEND
HSR.0
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this
bit prompts the user to read the THIR register for details.
NOTE:
The RBOC, RPE, RPS, and TMEND bits are latched and will be cleared when read.
HIMR: HDLC INTERRUPT MASK REGISTER (Address = 02 Hex)
(MSB)
(LSB)
RBOC
RPE
RPS
RHALF
RNE
THALF
TNF
TMEND
SYMBOL
POSITION
NAME AND DESCRIPTION
RBOC
HIMR.7
Receive BOC Detector Change of State.
0 = interrupt masked
1 = interrupt enabled
RPE
HIMR.6
Receive Packet End.
0 = interrupt masked
1 = interrupt enabled
RPS
HIMR.5
Receive Packet Start.
0 = interrupt masked
1 = interrupt enabled
RHALF
HIMR.4
Receive FIFO Half Full.
0 = interrupt masked
1 = interrupt enabled
RNE
HIMR.3
Receive FIFO Not Empty.
0 = interrupt masked
1 = interrupt enabled
THALF
HIMR.2
Transmit FIFO Half Empty.
0 = interrupt masked
1 = interrupt enabled
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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