參數(shù)資料
型號: DS21FF42N
廠商: DALLAS SEMICONDUCTOR
元件分類: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封裝: 27 X 27 MM, BGA-300
文件頁數(shù): 42/115頁
文件大?。?/td> 534K
代理商: DS21FF42N
DS21FF42/DS21FT42
32 of 115
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)
(LSB)
T1E1
0
ID3
ID2
ID1
ID0
SYMBOL
POSITION
NAME AND DESCRIPTION
T1E1
IDR.7
T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chip
ID3
IDR.3
Chip Revision Bit 3. MSB of a decimal code that represents
the chip revision.
ID2
IDR.1
Chip Revision Bit 2.
ID1
IDR.2
Chip Revision Bit 1.
ID0
IDR.0
Chip Revision Bit 0. LSB of a decimal code that represents
the chip revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB)
(LSB)
LCVCRF
ARC
OOF1
OOF2
SYNCC
SYNCT
SYNCE
RESYNC
SYMBOL
POSITION
NAME AND DESCRIPTION
LCVCRF
RCR1.7
Line Code Violation Count Register Function Select.
0 = do not count excessive zeros
1 = count excessive zeros
ARC
RCR1.6
Auto Resync Criteria.
0 = Resync on OOF or RCL event
1 = Resync on OOF only
OOF1
RCR1.5
Out Of Frame Select 1.
0 = 2/4 frame bits in error
1 = 2/5 frame bits in error
OOF2
RCR1.4
Out Of Frame Select 2.
0 = follow RCR1.5
1 = 2/6 frame bits in error
SYNCC
RCR1.3
Sync Criteria.
In D4 Framing Mode.
0 = search for Ft pattern, then search for Fs pattern
1 = cross couple Ft and Fs pattern
In ESF Framing Mode.
0 = search for FPS pattern only
1 = search for FPS and verify with CRC6
SYNCT
RCR1.2
Sync Time.
0 = qualify 10 bits
1 = qualify 24 bits
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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