參數(shù)資料
型號(hào): DS21FF42+
廠商: Maxim Integrated Products
文件頁數(shù): 94/114頁
文件大?。?/td> 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
80 of 114
RDNCD: RECEIVE DOWN CODE DEFINITION REGISTER (Address=15 Hex)
(MSB)
(LSB)
C7
C6
C5
C4
C3
C2
C1
C0
SYMBOL
POSITION
NAME AND DESCRIPTION
C7
RDNCD.7
Receive Down Code Definition Bit 7. First bit of the
repeating pattern.
C6
RDNCD.6
Receive Down Code Definition Bit 6. A Don’t Care if a 1
bit length is selected.
C5
RDNCD.5
Receive Down Code Definition Bit 5. A Don’t Care if a 1
or 2 bit length is selected.
C4
RDNCD.4
Receive Down Code Definition Bit 4. A Don’t Care if a 1
to 3 bit length is selected.
C3
RDNCD.3
Receive Down Code Definition Bit 3. A Don’t Care if a 1
to 4 bit length is selected.
C2
RDNCD.2
Receive Down Code Definition Bit 2. A Don’t Care if a 1
to 5 bit length is selected.
C1
RDNCD.1
Receive Down Code Definition Bit 1. A Don’t Care if a 1
to 6 bit length is selected.
C0
RDNCD.0
Receive Down Code Definition Bit 0. A Don’t Care if a 1
to 7 bit length is selected.
20.
TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of the framer can be either forced to be transparent or
in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting the data in
the channels. Transparency can be invoked on a channel by channel basis by properly setting the TTR1,
TTR2, and TTR3 registers.
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER
(Address=39 to 3B Hex)
(MSB)
(LSB)
CH8
CH7
CH6
CH5
CH4
CH3
CH2
CH1
TTR1 (39)
CH16
CH15
CH14
CH13
CH12
CH11
CH10
CH9
TTR2 (3A)
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
TTR3 (3B)
SYMBOLS
POSITIONS
NAME AND DESCRIPTION
CH1-24
TTR1.0-3.7
Transmit Transparency Registers.
0 = this DS0 channel is not transparent
1 = this DS0 channel is transparent
Each of the bit position in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represent a DS0
channel in the outgoing frame. When these bits are set to a one, the corresponding channel is transparent
(or clear). If a DS0 is programmed to be clear, no robbed bit signaling will be inserted nor will the
channel have Bit 7 stuffing performed. However, in the D4 framing mode, Bit 2 will be overwritten by a
zero when a Yellow Alarm is transmitted. Also the user has the option to prevent the TTR registers from
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