參數(shù)資料
型號(hào): DS21FF42+
廠商: Maxim Integrated Products
文件頁數(shù): 103/114頁
文件大?。?/td> 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 40
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應(yīng)商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
89 of 114
ID CODE STRUCTURE Table 22-2
MSB
LSB
Contents
Version
(Contact Factory)
Device ID
(See Table 23-3)
JEDEC
“00010100001”
“1”
Length
4 bits
16 bits
11 bits
1 bit
DEVICE ID CODES Table 22-3
DEVICE
16-BIT NUMBER
DS21Q42
0000h
DS21Q44
0001h
Highz
All digital outputs of the DS21Q42 will be placed in a high impedance state. The BYPASS register will
be connected between JTDI and JTDO.
Clamp
All digital outputs of the DS21Q42 will output data from the boundary scan parallel output while
connecting the bypass register between JTDI and JTDO. The outputs will not change during the CLAMP
instruction.
23.4 TEST REGISTERS
IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21Q42 design.
This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is 126 bits in length. Table 23-4 shows all of the cell bit locations and definitions.
Bypass Register
This is a single 1-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This
register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-
Reset state.
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