參數(shù)資料
型號: DS21FF42+
廠商: Maxim Integrated Products
文件頁數(shù): 28/114頁
文件大?。?/td> 0K
描述: IC FRAMER T1 4X4 16CH 300-BGA
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 40
控制器類型: T1 調(diào)幀器
接口: 并行/串行
電源電壓: 2.97 V ~ 3.63 V
電流 - 電源: 300mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 300-BBGA
供應商設(shè)備封裝: 300-PBGA(27x27)
包裝: 管件
DS21FT42/DS21FF42
20 of 114
Signal Name:
TLINK
Signal Description:
Transmit Link Data
Signal Type:
Input
If enabled via TCR1.2, this pin will be sampled on the falling edge of TCLK for data insertion into either
the FDL stream (ESF) or the Fs–bit position (D4) or the Z–bit position (ZBTSI). See Section 19 for
details. This signal is not bonded out in the DS21FF42/DS21FT42.
Signal Name:
TSYNC
Signal Description:
Transmit Sync
Signal Type:
Input /Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via
TCR2.2, the DS21Q42 can be programmed to output either a frame or multiframe pulse at this pin. If
this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double–wide
pulses at signaling frames. See Section 24 for details.
Signal Name:
TSSYNC
Signal Description:
Transmit System Sync
Signal Type:
Input
Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame
or multiframe boundaries for the transmit side. Should be tied low in applications that do not use the
transmit side elastic store.
Signal Name:
TSIG
Signal Description:
Transmit Signaling Input
Signal Type:
Input
When enabled, this input will sample signaling bits for insertion into outgoing PCM T1 data stream.
Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit side elastic store is enabled. This function is available when
FMS = 0. FMS is tied to ground for the DS21FF42/DS21FT42.
Signal Name:
TPOS
Signal Description:
Transmit Positive Data Output
Signal Type:
Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be
programmed to source NRZ data via the Output Data Format (CCR1.6) control bit.
Signal Name:
TNEG
Signal Description:
Transmit Negative Data Output
Signal Type:
Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter.
RECEIVE SIDE PINS
Signal Name:
RLINK
Signal Description:
Receive Link Data
Signal Type:
Output
Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a
frame. See Section 24 for details. This signal is not bonded out in the DS21FF42/DS21FT42.
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