參數(shù)資料
型號: DS2196L
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 56/157頁
文件大小: 734K
代理商: DS2196L
DS2196
56 of 157
RIR3A: RECEIVE INFORMATION REGISTER 3 FRAMER A (Address = 10
Hex)
(MSB)
RL1
(LSB)
RAIS-CI
RL0
JALT
LORC
LRCL
SYMBOL
POSITION
NAME AND DESCRIPTION
RL1
RL0
JALT
RIR3A.7
RIR3A.6
RIR3A.5
Receive Level Bit 1.
See Table 7–1.
Receive Level Bit 0.
See Table 7–1.
Jitter Attenuator Limit Trip.
Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
Loss of Receive Clock.
Set when the RCLKIA pin has not
transitioned for at least 2 s (3 s 1 s).
Line Interface Receive Carrier Loss.
Set when 192
consecutive zeros have been received at the RRING and RTIP
pins; allowed to be cleared when 14 or more 1’s out of 112
possible bit positions are received.
Not Assigned.
Could be any value when read.
Not Assigned.
Could be any value when read.
Receive AIS-CI Detect.
Set when the AIS-CI pattern is
detected. (see note below)
LORC
RIR3A.4
LRCL
RIR3A.3
RIR3A.2
RIR3A.1
RIR3A.0
RAIS-CI
RIR3B: RECEIVE INFORMATION REGISTER 3 FRAMER B
(Address = B0 Hex)
(MSB)
(LSB)
RAIS-CI
LORC
SYMBOL
POSITION
NAME AND DESCRIPTION
RIR3B.7
RIR3B.6
RIR3B.5
RIR3B.4
Not Assigned.
Could be any value when read.
Not Assigned.
Could be any value when read.
Not Assigned.
Could be any value when read.
Loss of Receive Clock.
Set when the RCLKIB pin has not
transitioned for at least 2 s(3 s 1 s).
Not Assigned.
Could be any value when read.
Not Assigned.
Could be any value when read.
Not Assigned.
Could be any value when read.
Receive AIS-CI Detect.
Set when the AIS-CI pattern is
detected. (see note below)
LORC
RIR3B.3
RIR3B.2
RIR3B.1
RIR3A.0
RAIS-CI
相關(guān)PDF資料
PDF描述
DS2196LN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43AT Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43ATN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44T Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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