參數(shù)資料
型號: DS2196L
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 18/157頁
文件大?。?/td> 734K
代理商: DS2196L
DS2196
18 of 157
Signal Type:
This digital output will provide either a frame synchronization pulse or the negative half of a bipolar data stream.
The signal is based on what is provided at the TNEGLI input.
Output
Signal Name:
Signal Description:
Signal Type:
This digital output will provide either a NRZ data stream or the positive half of a bipolar data stream. The signal is
based on what is provided at the TPOSLI input.
LNRZ
LIU NRZ Data
Output
Signal Name:
Signal Description:
Signal Type:
This digital output provides the 1.544 MHz transmit LIU clock. The signal is based on what is provided at the
TCLKLI input.
LCLK
LIU Clock
Output
Signal Name:
Signal Description:
Signal Type:
This digital input is used to pass either the negative half of a bipolar data stream or a frame synchronization pulse
via the jitter attenuator block to the transmit line driver block and the LFSYNC output pin. Data input to this pin is
sampled on the falling edge of TCLKLI. TNEGLI can be internally connected to TNEGOA/TFSYNCA via the
CCR4A.2 control bit.
TNEGLI
Transmit Negative Data for the LIU
Input
Signal Name:
Signal Description:
Signal Type:
This digital input is used to pass either the positive half of a bipolar data stream or a NRZ data stream via the jitter
attenuator block to the transmit line driver block and the LNRZ output pin. Data input to this pin is sampled on the
falling edge of TCLKLI. TPOSLI can be internally connected to TPOSOA/TNRZA via the CCR4A.2 control bit.
TPOSLI
Transmit Positive Data for the LIU
Input
Signal Name:
Signal Description:
Signal Type:
This digital input is used to pass a 1.544 MHz clock via the jitter attenuator block to the transmit line driver block
and the LCLK output pin. TCLKLI can be internally connected to TCLKOA via the CCR4A.2 control bit.
TCLKLI
Transmit Clock for the LIU
Input
Signal Name:
Signal Description:
Signal Type:
This digital input is used to pass a NRZ data stream via the Data Source Selection MUX and the jitter attenuator
block to the RPOSLO and RNEGLO output pins. Data input to this pin is sampled on the falling or rising edge of
WCLK.
WNRZ
Working NRZ Data
Input
Signal Name:
Signal Description:
Signal Type:
This digital input is used to pass a 1.544 MHz clock via the Data Source Selection MUX and the jitter attenuator
block to the RCLKLO output pin.
WCLK
Working Clock
Input
相關(guān)PDF資料
PDF描述
DS2196LN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43AT Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43ATN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44T Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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參數(shù)描述
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