參數(shù)資料
型號: DS2196L
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 49/157頁
文件大小: 734K
代理商: DS2196L
DS2196
49 of 157
CCR7A: COMMON CONTROL REGISTER 7 FRAMER A (Address = 0A Hex)
(MSB)
LIRST
(LSB)
LBOS3
RLB
AIS13-24
AIS1-12
DISRCL
SYMBOL
POSITION
NAME AND DESCRIPTION
LIRST
CCR7A.7
Line Interface reset.
Setting this bit from a 0 to a 1 will
initiate an internal reset that affects the clock recovery state
machine and jitter attenuator. Normally this bit is only toggled
on power–up. Must be cleared and set again for a subsequent
reset.
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
Channels 13 – 24 AIS Enable
0 = do not transmit AIS in channels 13 – 24
1 = transmit AIS in channels 13 - 24
Channels 1 – 12 AIS Enable
0 = do not transmit AIS in channels 1 – 12
1 = transmit AIS in channels 1 - 12
LIU Receive Carrier Loss (RCL) pin Disable.
0 = Normal operation.
1 = Disable the LIU RCL pin. Pin will always output a “0”.
The LRCL status bit in RIR3A.3 continues to report correct
LRCL status.
Not Assigned.
Should be set to 0 when written to.
Not Assigned.
Should be set to 0 when written to.
Line Build Out Select Bit 3.
Sets the transmitter build out; see
the Table 19–1
RLB
CCR7A.6
AIS13-24
CCR7A.5
AIS1-12
CCR7A.4
DISRCL
CCR7A.3
CCR7A.2
CCR7A.1
CCR7A.0
LBOS3
相關(guān)PDF資料
PDF描述
DS2196LN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43AT Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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