參數(shù)資料
型號: DS2196L
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 17/157頁
文件大?。?/td> 734K
代理商: DS2196L
DS2196
17 of 157
Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, this
pin should be pulled high.
JTCLK
JTAG IEEE 1149.1 Test Serial Clock
Input
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this pin should be
pulled high. This pin has an internal pull-up.
JTDI
JTAG IEEE 1149.1 Test Serial Data Input
Input
Signal Name:
Signal Description:
Signal Type:
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this pin should be left
open circuited.
JTDO
JTAG IEEE 1149.1 Test Serial Data Output
Output
Signal Name:
Signal Description:
Signal Type:
This signal is used to synchronously reset the test access port controller. At power up, JTRST must be set low and
then high. This action will set the device into the boundary scan bypass mode allowing normal device operation.
If boundary scan is not used, this pin should be held low. This pin has an internal pull-up.
JTRST*
JTAG IEEE 1149.1 Test Reset
Input
Signal Name:
Signal Description:
Signal Type:
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE
1149.1 states. If not used, this pin should be pulled high. This signal has an internal pull-up.
JTMS
JTAG IEEE 1149.1 Test Mode Select
Input
Line Interface Pins
Signal Name:
Signal Description:
Signal Type:
A 1.544 MHz (±50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. This clock is also used to source AIS within the LIU.
MCLK
Master Clock Input
Input
Signal Name:
Signal Description:
Signal Type:
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the T1 line. See Section 19
for details.
RTIP & RRING
Receive Tip and Ring
Input
Signal Name:
Signal Description:
Signal Type:
Analog line driver outputs. These pins connect via a 1:2 step–up transformer to the T1 line. See Section 19 for
details.
TTIP & TRING
Transmit Tip and Ring
Output
Signal Name:
Signal Description:
LFSYNC
LIU Frame Sync
相關(guān)PDF資料
PDF描述
DS2196LN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43AT Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q43ATN Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
DS21Q44T Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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DS2196LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Dual Framer LIU RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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