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參數(shù)資料
| 型號： | DS2180A |
| 廠商： | DALLAS SEMICONDUCTOR |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | T1 Transceiver(T1收發(fā)器) |
| 中文描述： | DATACOM, FRAMER, PDIP40 |
| 封裝： | 0.600 INCH, DIP-40 |
| 文件頁數(shù)： | 3/35頁 |
| 文件大小： | 232K |
| 代理商： | DS2180A |
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DS2180A
022798 3/35
TRANSMIT PIN DESCRIPTION (40–PIN DIP ONLY)
Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
TMSYNC
I
Transmit Multiframe Sync.
May be pulsed high at multiframe boundaries
to reinforce multiframe alignment or tied low, which allows internal multiframe
counter to free run.
2
TFSYNC
I
Transmit Frame Sync.
Rising edge identifies frame boundary; may be
pulsed every frame to reinforce internal frame counter or tied low (allowing
TMSYNC to establish frame and multiframe alignment).
3
TCLK
I
Transmit Clock.
1.544 MHz primary clock.
4
TCHCLK
O
Transmit Channel Clock.
192 KHz clock which identifies time slot (channel)
boundaries. Useful for parallel-to-serial conversion of channel data.
5
TSER
I
Transmit Serial Data.
NRZ data input, sample on falling edge of TCLK.
6
TMO
O
Transmit Multiframe Out.
Output of internal multiframe counter indicates
multiframe boundaries. 50% duty cycle.
7
TSIGSEL
O
Transmit Signaling Select.
.667 KHz clock which identifies signaling frame
A and C in 193E framing. 1.33 KHz clock in 193S.
8
TSIGFR
O
Transmit Signaling Frame.
High during signaling frames, low otherwise.
9
TABCD
I
Transmit ABCD Signaling.
When enabled via TCR.4, sampled during
channel LSB time in signaling frames on falling edge of TCLK.
10
TLINK
I
Transmit Link Data.
Sampled during the F-bit time (falling edge of TCLK) of
odd frames for insertion into the outgoing data stream (193E-FDL insertion).
Sampled during the F-bit time of even frames for insertion into the outgoing
data (193S-External S-Bit insertion).
11
TLCLK
O
Transmit Link Clock.
4 KHz demand clock for TLINK input.
12
13
TPOS
TNEG
O
Transmit Bipolar Data Outputs.
Updated on rising edge of TCLK.
PORT PIN DESCRIPTION (40–PIN DIP ONLY)
Table 2
PIN
SYMBOL
TYPE
DESCRIPTION
14
INT
1
O
Receive Alarm Interrupt.
Flags host controller during alarm conditions. Ac-
tive low, open drain output.
15
SDI
1
I
Serial Data In.
Data for onboard registers. Sampled on rising edge of SCLK.
16
SDO
1
O
Serial Data Out.
Control and status information from onboard registers. Up-
dated on falling edge of SCLK, tri-stated during serial port write or when CS
is high.
17
CS
1
I
Chip Select.
Must be low to write or read the serial port registers.
18
SCLK
1
I
Serial Data Clock.
Used to write or read the serial port registers.
19
SPS
I
Serial Port Select.
Tie to V
DD
to select serial port. Tie to V
SS
to select hard-
ware mode.
NOTE:
1. Multifunction pins. See “Hardware Mode Description.”
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS2180A+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2180AN | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2180AQ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS2180AQ/T&R | 制造商:Maxim Integrated Products 功能描述:T1 TRANSCEIVER-PLCC-TRL - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC TRANSCEIVER T1 44-PLCC 制造商:Maxim Integrated Products 功能描述:Network Controller & Processor ICs T1 Transceiver |
| DS2180AQ/T&R+ | 制造商:Maxim Integrated Products 功能描述:T1 TRANSCEIVER PLCC TRL LF - Tape and Reel |
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