參數(shù)資料
型號: DS21554LN+
廠商: Maxim Integrated Products
文件頁數(shù): 15/124頁
文件大?。?/td> 0K
描述: IC TXRX E1 1-CHIP 5V 100-LQFP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC,J1,T1
電路數(shù): 1
電源電壓: 4.75 V ~ 5.25 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: 遠程和 AIS 警報檢測器 / 發(fā)生器
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
111 of 124
19.
OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground………………………………………………………………-1.0V to +6.0V
Operating Temperature Range for DS21354L/DS21554L……………………………………………………0°C to +70°C
Operating Temperature Range for DS21354LN/DS21554LN……………………………………………..-40°C to +85°C
Storage Temperature Range………………………………………………………………………………...-55°C to +125°C
Soldering Temperature………………………………………………………..See IPC/JEDEC J-STD-020A Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device
reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VDD = 3.3V
±5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V ±5%, TA = 0°C to +70°C for DS21554L;
VDD = 3.3V
±5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V ±5%, TA = -40°C to +85°C for DS21554LN.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Logic 1
VIH
2.0
5.5
V
Logic 0
VIL
–0.3
+0.8
V
Supply for DS21354
VDD
3.135
3.3
3.465
V
1
Supply for DS21554
VDD
4.75
5
5.25
V
1
CAPACITANCE
(TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Capacitance
CIN
5
pF
Output Capacitance
COUT
7
pF
DC CHARACTERISTICS
(VDD = 3.3V
±5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V ±5%, TA = 0°C to +70°C for DS21554L;
VDD = 3.3V
±5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V ±5%, TA = -40°C to +85°C for DS21554LN.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Supply Current at 5V
IDD
75
mA
2
Supply Current at 3.3V
IDD
75
mA
2
Input Leakage
IIL
–1.0
+1.0
mA
3
Output Leakage
ILO
1.0
mA
4
Output Current (2.4V)
IOH
–1.0
mA
Output Current (0.4V)
IOL
+4.0
mA
Note 1:
Applies to RVDD, TVDD, and DVDD.
Note 2:
TCLK = TCLKI = RCLKI = TSYSCLK = RSYSCLK = MCLK = 2.048MHz; outputs open circuited.
Note 3:
0.0V < VIN < VDD.
Note 4:
Applied to
INT when tri-stated.
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