參數(shù)資料
型號: DS2154L
英文描述: Enhanced E1 Single Chip Transceiver
中文描述: 增強素E1單芯片收發(fā)器
文件頁數(shù): 11/87頁
文件大?。?/td> 1106K
代理商: DS2154L
DS2154
11 of 87
Transmit Data [TDATA].
Sampled on the falling edge of TCLK with data to be clocked through the
transmit side formatter. This pin is normally tied to TESO.
Transmit Positive Data Output [TPOSO].
Updated on the rising edge of TCLKO with the bipolar data
out of the transmit side formatter. Can be programmed to source NRZ data via the Output Data Format
(TCR1.7) control bit. This pin is normally tied to TPOSI.
Transmit Negative Data Output [TNEGO].
Updated on the rising edge of TCLKO with the bipolar
data out of the transmit side formatter. This pin is normally tied to TNEGI.
Transmit Clock Output [TCLKO].
Buffered clock that is used to clock data through the transmit side
formatter (i.e. either TCLK or RCLKO if Loss Of Transmit Clock is enabled and in effect or RCLKI if
remote loopback is enabled). This pin is normally tied to TCLKI.
Transmit Positive Data Input [TPOSI].
Sampled on the falling edge of TCLKI for data to be
transmitted out onto the E1 line. Can be internally connected to TPOSO by tying the LIUC pin high.
Transmit Negative Data Input [TNEGI].
Sampled on the falling edge of TCLKI for data to be
transmitted out onto the E1 line. Can be internally connected to TNEGO by tying the LIUC pin high.
Transmit Clock Input [TCLKI].
Line interface transmit clock. Can be internally connected to TCLKO
by tying the LIUC pin high.
RECEIVE SIDE DIGITAL PINS
Receive Link Data [RLINK].
Updated with the full recovered E1 data stream on the rising edge of
RCLK.
Receive Link Clock [RLCLK].
4 kHz to 20 kHz clock (Sa bits) for the RLINK output. See Section 11
for details.
Receive Clock [RCLK].
2.048 MHz clock that is used to clock data through the receive side framer.
Receive Channel Clock [RCHCLK].
256 kHz clock which pulses high during the LSB of each channel.
Synchronous with RCLK when the receive side elastic store is disabled. Synchronous with RSYSCLK
when the receive side elastic store is enabled. Useful for parallel to serial conversion of channel data.
Receive Channel Block [RCHBLK].
A user-programmable output that can be forced high or low during
any of the 32 E1 channels. Synchronous with RCLK when the receive side elastic store is disabled.
Synchronous with RSYSCLK when the receive side elastic store is enabled. Useful for blocking clocks to
a serial UART or LAPD controller in applications where not all E1 channels are used such as Fractional
E1, 384k bps service, 768k bps, or ISDN-PRI. Also useful for locating individual channels in drop-and-
insert applications, for external per-channel loopback, and for per-channel conditioning. See Section 9 for
details.
Receive Serial Data [RSER].
Received NRZ serial data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive side
elastic store is enabled.
相關(guān)PDF資料
PDF描述
DS2154LN Enhanced E1 Single Chip Transceiver
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS2154L+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2154LA2 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2154LA2+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS2154L-C01 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS2154LD1 功能描述:網(wǎng)絡(luò)控制器與處理器 IC Enhanced E1 Transceiver RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray