參數(shù)資料
型號(hào): DS21354LC1+
廠商: Maxim Integrated Products
文件頁數(shù): 67/124頁
文件大?。?/td> 0K
描述: IC TXRX E1 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: 遠(yuǎn)程和 AIS 警報(bào)檢測(cè)器 / 發(fā)生器
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
47 of 124
SR2: STATUS REGISTER 2 (Address = 07 Hex)
(MSB)
(LSB)
RMF
RAF
TMF
SEC
TAF
LOTC
RCMF
TSLIP
SYMBOL
POSITION
NAME AND DESCRIPTION
RMF
SR2.7
Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is
enabled or not) on receive multiframe boundaries. Used to alert the host
that signaling data is available.
RAF
SR2.6
Receive Align Frame. Set every 250ns at the beginning of align frames.
Used to alert the host that Si and Sa bits are available in the RAF and
RNAF registers.
TMF
SR2.5
Transmit Multiframe. Set every 2ms (regardless if CRC4 is enabled) on
transmit multiframe boundaries. Used to alert the host that signaling data
needs to be updated.
SEC
SR2.4
One Second Timer. Set on increments of one second based on RCLK. If
CCR2.7=1, then this bit will be set every 62.5ms instead of once a
second.
TAF
SR2.3
Transmit Align Frame. Set every 250ns at the beginning of align
frames. Used to alert the host that the TAF and TNAF registers need to
be updated.
LOTC
SR2.2
Loss of Transmit Clock. Set when the TCLK pin has not transitioned
for one channel time (or 3. ns). Will force the LOTC pin high if enabled
via TCR2.0.
RCMF
SR2.1
Receive CRC4 Multiframe. Set on CRC4 multiframe boundaries; will
continue to be set every 2ms on an arbitrary boundary if CRC4 is
disabled.
TSLIP
SR2.0
Transmit Elastic Store Slip. Set when the elastic store has either
repeated or deleted a frame of data.
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