參數(shù)資料
型號: DS21354LC1+
廠商: Maxim Integrated Products
文件頁數(shù): 35/124頁
文件大小: 0K
描述: IC TXRX E1 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
功能: 單芯片收發(fā)器
接口: E1,HDLC
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 75mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: 遠(yuǎn)程和 AIS 警報(bào)檢測器 / 發(fā)生器
產(chǎn)品目錄頁面: 1430 (CN2011-ZH PDF)
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
18 of 124
Signal Name:
RFSYNC
Signal Description:
Receive Frame Sync
Signal Type:
Output
An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries.
Signal Name:
RMSYNC
Signal Description:
Receive Multiframe Sync
Signal Type:
Output
If the receive-side elastic store is enabled, an extracted pulse, one RSYSCLK wide, is output at this pin
that identifies multiframe boundaries. If the receive-side elastic store is disabled, then this output will
output multiframe boundaries associated with RCLK.
Signal Name:
RDATA
Signal Description:
Receive Data
Signal Type:
Output
Updated on the rising edge of RCLK with the data out of the receive-side framer.
Signal Name:
RSYSCLK
Signal Description:
Receive System Clock
Signal Type:
Input
1.544MHz, 2.048MHz, 4.096MHz, or 8.192MHz clock. Only used when the receive-side elastic store
function is enabled. Should be tied low in applications that do not use the receive-side elastic store. See
Section 17 for details on 4.096MHz and 8.192MHz operation using the Interleave Bus Option.
Signal Name:
RSIG
Signal Description:
Receive Signaling Output
Signal Type:
Output
Outputs signaling bits in a PCM format. Updated on rising edges of RCLK when the receive-side elastic
store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled.
Signal Name:
RLOS/LOTC
Signal Description:
Receive Loss of Sync / Loss of Transmit Clock
Signal Type:
Output
A dual function output that is controlled by the TCR2.0 control bit. This pin can be programmed to either
toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the
TCLK pin has not been toggled for 5
ms.
Signal Name:
RCL
Signal Description:
Receive Carrier Loss
Signal Type:
Output
Set high when the line interface detects a carrier loss.
Signal Name:
RSIGF
Signal Description:
Receive Signaling Freeze
Signal Type:
Output
Set high when the signaling data is frozen via either automatic or manual intervention. Used to alert
downstream equipment of the condition.
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DS21372 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:3.3V Bit Error Rate Tester BERT
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