TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex) (MSB) (LSB) " />
參數(shù)資料
型號(hào)： DS21352LN
廠商： Maxim Integrated Products
文件頁數(shù)： 92/137頁
文件大?。?/td> 0K
描述： IC TXRX T1 1-CHIP 3.3V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
產(chǎn)品變化通告： Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝： 90
功能： 單芯片收發(fā)器
接口： HDLC，T1
電路數(shù)： 1
電源電壓： 3.14 V ~ 3.47 V
電流 - 電源： 75mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
包括： DSX-1 和 CSU 線路補(bǔ)償發(fā)生器，HDLC 控制器，帶內(nèi)回路代碼發(fā)生器和檢測(cè)器
DS21352/DS21552
58 of 137
TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex)
(MSB)
(LSB)
A(8)
A(7)
A(6)
A(5)
A(4)
A(3)
A(2)
A(1)
TS1 (70)
A(16)
A(15)
A(14)
A(13)
A(12)
A(11)
A(10)
A(9)
TS2 (71)
A(24)
A(23)
A(22)
A(21)
A(20)
A(19)
A(18)
A(17)
TS3 (72)
B(8)
B(7)
B(6)
B(5)
B(4)
B(3)
B(2)
B(1)
TS4 (73)
B(16)
B(15)
B(14)
B(13)
B(12)
B(11)
B(10)
B(9)
TS5 (74)
B(24)
B(23)
B(22)
B(21)
B(20)
B(19)
B(18)
B(17)
TS7 (75)
A/C(8)
A/C(7)
A/C(6)
A/C(5)
A/C(4)
A/C(3)
A/C(2)
A/C(1)
TS7 (76)
A/C(16)
A/C(15)
A/C(14)
A/C(13)
A/C(12)
A/C(11)
A/C(10)
A/C(9)
TS8 (77)
A/C(24)
A/C(23)
A/C(22)
A/C(21)
A/C(20)
A/C(19)
A/C(18)
A/C(17)
TS9 (78)
B/D(8)
B/D(7)
B/D(6)
B/D(5)
B/D(4)
B/D(3)
B/D(2)
B/D(1)
TS10 (79)
B/D(16)
B/D(15)
B/D(14)
B/D(13)
B/D(12)
B/D(11)
B/D(10)
B/D(9)
TS11 (7A)
B/D(24)
B/D(23)
B/D(22)
B/D(21)
B/D(20)
B/D(19)
B/D(18)
B/D(17)
TS12 (7B)
SYMBOL
POSITION
NAME AND DESCRIPTION
D(24)
TS12.7
Signaling Bit D in Channel 24
A(1)
TS1.0
Signaling Bit A in Channel 1
Each Transmit Signaling Register (TS1 to TS12) contains the Robbed Bit signaling for eight DS0
channels that will be inserted into the outgoing stream if enabled to do so via TCR1.4. In the ESF framing
mode, there can be up to four signaling bits per channel (A, B, C, and D). On multiframe boundaries, the
framer will load the values present in the Transmit Signaling Register into an outgoing signaling shift
register that is internal to the device. The user can utilize the Transmit Multiframe Interrupt in Status
Register 2 (SR2.6) to know when to update the signaling bits. In the ESF framing mode, the interrupt will
come every 3 ms and the user has a full 3ms to update the TSRs. In the D4 framing mode, there are only
two signaling bits per channel (A and B). However in the D4 framing mode, the framer uses the C and D
bit positions as the A and B bit positions for the next multiframe. The framer will load the values in the
TSRs into the outgoing shift register every other D4 multiframe.
10.2 HARDWARE BASED SIGNALING
10.2.1 RECEIVE SIDE
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer; signaling extraction and signaling re–insertion. Signaling extraction involves pulling the signaling
bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in
a serial PCM fashion on a channel–by–channel basis at the RSIG output. This mode is always enabled. In
this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then
the backplane clock (RSYSCLK) can be either 1.544 MHz or 2.048 MHz. In the ESF framing mode, the
ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated
once a multiframe (3 ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are
output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as
bits 7 and 8 respectively in each channel. The RSIG data is updated once a multiframe (1.5 ms) unless a
freeze is in effect. See the timing diagrams in Section 21 for some examples.
10.2.1.1 RECEIVE SIGNALING RE-INSERTION
The other hardware based signaling operating mode called signaling re–insertion can be invoked by
setting the RSRE control bit high (CCR4.7=1). In this mode, the user will provide a multiframe sync at
the RSYNC pin and the signaling data will be re–aligned at the RSER output according to this applied
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS21352LN+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC T1 Single Chip Transceivers RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21354 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:3.3V/5V E1 Single-Chip Transceivers
DS21354DK 功能描述:網(wǎng)絡(luò)開發(fā)工具 DS21354 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 產(chǎn)品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評(píng)估:RCM6600W 數(shù)據(jù)速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V
DS21354G 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS21354GN 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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