參數(shù)資料
型號: DS21352LN
廠商: Maxim Integrated Products
文件頁數(shù): 64/137頁
文件大?。?/td> 0K
描述: IC TXRX T1 1-CHIP 3.3V 100-LQFP
產品培訓模塊: Lead (SnPb) Finish for COTS
產品變化通告: Product Discontinuation 20/Feb/2012
標準包裝: 90
功能: 單芯片收發(fā)器
接口: HDLC,T1
電路數(shù): 1
電源電壓: 3.14 V ~ 3.47 V
電流 - 電源: 75mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應商設備封裝: 100-LQFP(14x14)
包裝: 托盤
包括: DSX-1 和 CSU 線路補償發(fā)生器,HDLC 控制器,帶內回路代碼發(fā)生器和檢測器
DS21352/DS21552
32 of 137
RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex)
(MSB)
(LSB)
RCS
RZBTSI
RSDW
RSM
RSIO
RD4YM
FSBE
MOSCRF
SYMBOL
POSITION
NAME AND DESCRIPTION
RCS
RCR2.7
Receive Code Select.
0 = idle code (7F Hex)
1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex)
RZBTSI
RCR2.6
Receive Side ZBTSI Support Enable. Allows ZBTSI information to be output on
RLINK pin.
0 = ZBTSI disabled
1 = ZBTSI enabled
RSDW
RCR2.5
RSYNC Double–Wide. (note: this bit must be set to zero when RCR2.4 = 1 or when
RCR2.3 = 1)
0 = do not pulse double wide in signaling frames
1 = do pulse double wide in signaling frames
RSM
RCR2.4
RSYNC Mode Select. Selects frame or multiframe pulse when RSYNC pin is in output
mode. In input mode (elastic store must be enabled) multiframe mode is only useful
when receive signaling re-insertion is enabled. See the timing in Section 21.
0 = frame mode
1 = multiframe mode
RSIO
RCR2.3
RSYNC I/O Select. (note: this bit must be set to zero when CCR1.2 = 0)
0 = RSYNC is an output
1 = RSYNC is an input (only valid if elastic store enabled)
RD4YM
RCR2.2
Receive Side D4 Yellow Alarm Select.
0 = zeros in bit 2 of all channels
1 = a one in the S–bit position of frame 12
FSBE
RCR2.1
PCVCR Fs–Bit Error Report Enable.
0 = do not report bit errors in Fs–bit position; only Ft bit position
1 = report bit errors in Fs–bit position as well as Ft bit position
MOSCRF
RCR2.0
Multiframe Out of Sync Count Register Function Select.
0 = count errors in the framing bit position
1 = count the number of multiframes out of sync
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