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參數(shù)資料
| 型號(hào)： | DS2045W |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 3.3V Single-Piece 1Mb Nonvolatile SRAM |
| 中文描述： | 3.3V、單芯片、1Mb非易失SRAM |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大小： | 207K |
| 代理商： | DS2045W |
D
DS2045W 3.3V Single-Piece 1Mb
Nonvolatile SRAM
6
_____________________________________________________________________
Power-Down/Power-Up Condition
t
DR
t
PU
t
F
t
PD
t
RPU
t
RPD
SLEWS WITH
V
CC
t
R
V
OL
V
IH
V
OL
t
REC
V
CC
V
TP
~
2.5V
CE,
WE
RST
BACKUP CURRENT
SUPPLIED FROM
LITHIUM BATTERY
(SEE NOTES 1, 7.)
Note 1:
RST
is an open-drain output and cannot source current. An external pullup resistor should be connected to this pin to real-
ize a logic-high level.
These parameters are sampled with a 5pF load and are not 100% tested.
t
WP
is specified as the logical AND of
CE
and
WE
. t
WP
is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
t
WR1
and t
DH1
are measured from
WE
going high.
t
WR2
and t
DH2
are measured from
CE
going high.
t
DS
is measured from the earlier of
CE
or
WE
going high.
In a power-down condition, the voltage on any pin can not exceed the voltage on V
CC
.
The expected t
DR
is defined as accumulative time in the absence of V
CC
starting from the time power is first applied by the
user. Minimum expected data-retention time is based on a maximum of two +230°C convection solder reflow exposures,
followed by a fully charged cell. Full charge occurs with the initial application of V
CC
for a minimum of 96 hours. This para-
meter is assured by component selection, process control, and design. It is not measured directly in production testing.
WE
is high for a read cycle.
Note 10:
OE
= V
IH
or V
IL
. If
OE
= V
IH
during write cycle, the output buffers remain in a high-impedance state.
Note 11:
If the
CE
low transition occurs simultaneously with or latter than the
WE
low transition, the output buffers remain in a high-
impedance state during this period.
Note 12:
If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output buffers remain in a high-
impedance state during this period.
Note 13:
If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition, the output buffers remain
in a high-impedance state during this period.
Note 14:
DS2045W BGA modules are recognized by Underwriters Laboratory (UL) under file E99151.
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| DS2045W-100 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS2045W-100# | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS2045Y | 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:Single-Piece 1Mb Nonvolatile SRAM |
| DS2045Y-100 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| DS2045Y-100# | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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