參數(shù)資料
型號(hào)： DS1920
廠商： Maxim Integrated Products, Inc.
英文描述： Temperature Button(溫度按鈕)
文件頁(yè)數(shù)： 25/52頁(yè)
文件大?。?/td> 881K
代理商： DS1920
AD14160/AD14160L
–25–
REV. A
40 MHz–5 V
40 MHz–3.3 V
Min
Parameter
Min
Max
Max
Units
Lead Cycle
Timing Requirements:
t
SADRDL
t
HADRDH
t
WRWH
t
DRDHRDY
t
DRDHRDY
Address Setup/
CS
Low Before
RD
Low
1
Address Hold/
CS
Hold Low After
RD
RD
/
WR
High Width
RD
High Delay After REDY (O/D) Disable
RD
High Delay After REDY (A/D) Disable
1
1
6
0.5
0.5
1
1
6
0.5
0.5
ns
ns
ns
ns
ns
Switching Characteristics:
t
SDATRDY
t
DRDYRDL
t
RDYPRD
t
HDARWH
Data Valid Before REDY Disable from Low
REDY (O/D) or (A/D) Low Delay After
RD
Low
REDY (O/D) or (A/D) Low Pulsewidth for Read
Data Disable After
RD
High
1
1
ns
ns
ns
ns
11
11.5
45 + DT
2
45 + DT
2
9.5
10
Write Cycle
Timing Requirements:
t
SCSWRL
t
HCSWRH
t
SADWRH
t
HADWRH
t
WWRL
t
WRWH
t
DWRHRDY
t
SDATWH
t
HDATWH
CS
Low Setup Before
WR
Low
CS
Low Hold After
WR
High
Address Setup Before
WR
High
Address Hold After
WR
High
WR
Low Width
RD
/
WR
High Width
WR
High Delay After REDY (O/D) or (A/D) Disable
Data Setup Before
WR
High
Data Hold After
WR
High
0
0.5
6
2.5
7
6
0.5
6
1.5
0
0.5
6
2.5
7
6
0.5
6
1.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
Switching Characteristics:
t
DRDYWRL
t
RDYPWR
t
SRDYCK
REDY (O/D) or (A/D) Low Delay After
WR
/
CS
Low
REDY (O/D) or (A/D) Low Pulsewidth for Write
REDY (O/D) or (A/D) Disable to CLKIN
11
11.5
ns
ns
ns
15
0.5 + 7DT/16 8 + 7DT/16
15
0.5 + 7DT/16
8 + 7DT/16
NOTE
1
Not required if
RD
and address are valid t
after
HBG
goes low. For first access after
HBR
asserted, ADDR
must be a non-MMS value 1/2 t
before
RD
or
WR
goes low or by t
after
HBG
goes low. This is easily accomplished by driving an upper address signal high when
HBG
is asserted. For address bits to be
driven during asynchronous host accesses, see Table 8.2 of the
ADSP-2106x SHARC User’s Manual
.
CLKIN
REDY (O/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
t
SRDYCK
REDY (A/D)
Figure 19a. Synchronous REDY Timing
Asynchronous Read/Write—Host to AD14160/AD14160L
Use these specifications for asynchronous host processor accesses
of an AD14160/AD14160L, after the host has asserted
CS
and
HBR
(low). After
HBG
is returned by the AD14160/AD14160L,
the host can drive the
RD
and
WR
pins to access the AD14160/
AD14160L’s internal memory or IOP registers.
HBR
and
HBG
are assumed low for this timing.
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