參數(shù)資料
型號: DS1267
廠商: Maxim Integrated Products, Inc.
元件分類: 數(shù)字電位計
英文描述: Dual Digital Potentiometer Chip(雙路數(shù)字電位器芯片)
中文描述: ±5V、雙路、數(shù)字電位器芯片
文件頁數(shù): 4/11頁
文件大?。?/td> 110K
代理商: DS1267
DS1267
022698 4/11
CASCADE OPERATION
A feature of the DS1267 is the ability to control multiple
devices from a single processor. Multiple DS1267s can
be linked or daisy chained as shown in Figure 4. As a
data bit is entered into the I/O shift register of the DS1267
a bit will appear at the C
OUT
output after a minimum delay
of 50 nanoseconds. The stack select bit of the DS1267
will always be the first out the part at the beginning of a
transaction. Additionally the C
OUT
pin is always active
regardless of the state of RST. This allows one to read
the I/O shift register without changing its value.
CASCADING MULTIPLE DEVICES
Figure 4
DS1267
#1
DS1267
#2
DS1267
#n
PROCESSOR
DQ
DQ
DQ
C
OUT
C
OUT
C
OUT
OPTIONAL FEEDBACK RESISTOR
FOR READING DATA (2K TO 10K)
The C
OUT
output of the DS1267 can be used to drive the
DQ input of another DS1267. When connecting multiple
devices, the total number of bits transmitted is always 17
times the number of DS1267s in the daisy chain.
An optional feedback resistor can be placed between the
C
OUT
terminal of the last device and the first DS1267 DQ
input thus allowing the controlling processor to read, as
well as, write data, or circularly clock data through the
daisy chain. The value of the feedback or isolation resis-
tor should be in the range from 1K to 10K ohms.
When reading data via the C
OUT
pin and isolation resis-
tor, the DQ line is left floating by the reading device.
When RST is driven high, bit 17 is present on the C
OUT
pin, which is fed back to the input DQ pin through the
isolation resistor. When the CLK input transitions low to
high, bit 17 is loaded into the first position of the I/O shift
register and bit 16 becomes present on C
OUT
and DQ of
the next device. After 17 bits (or 17 times the number of
DS1267s in the daisy chain), the data has shifted com-
pletely around and back to its original position. When
RST transitions to the low state to end data transfer, the
value (the same as before the read occurred) is loaded
into the wiper–0, wiper–1, and stack select bit I/O regis-
ter.
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity is defined as the difference between
the actual measured output voltage and the expected
output voltage. Figure 5 presents the test circuit used to
measure absolute inearity. Absolute linearity is given in
terms of a minimum increment or expected output when
the wiper is moved one position. In the case of the test
circuit, a minimum increment (MI) or one LSB would
equal 10/512 volts. The equation for absolute linearity is
given as follows:
(1)
ABSOLUTE LINEARITY
AL={V
O
(actual) – V
O
(expected)}/MI
Relative Linearity is a measure of error between two
adjacent wiper position points and is given in terms of MI
by equation (2).
(2)
RELATIVE LINEARITY
RL={V
O
(n+1) – V
O
(n)}/MI
Figure 6 is a plot of absolute linearity and relative inearity
versus wiper position for the DS1267 at 25
°
C. The spec-
ification for absolute linearity of the DS1267 is
±
0.75 MI
typical. The specification for relative linearity of the
DS1267 is
±
0.3 MI typical.
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