參數(shù)資料
型號: DS1267
廠商: Maxim Integrated Products, Inc.
元件分類: 數(shù)字電位計
英文描述: Dual Digital Potentiometer Chip(雙路數(shù)字電位器芯片)
中文描述: ±5V、雙路、數(shù)字電位器芯片
文件頁數(shù): 2/11頁
文件大?。?/td> 110K
代理商: DS1267
DS1267
022698 2/11
The DS1267 is offered in three standard resistance val-
ues which include 10K, 50K, and 100K ohm versions.
Commercial and industrial temperature parts are also
available. Available packages for the device include a
14–pin DIP, 16–pin SOIC, and 20–pin TSSOP.
OPERATION
The DS1267 contains two 256–position potentiometers
whose wiper positions are set by an 8–bit value. These
two 8–bit values are written to a 17–bit I/O shift register
which is used to store the two wiper positions and the
stack select bit when the device is powered. A block dia-
gram of the DS1267 is presented in Figure 1.
Communication and control of the DS1267 is accom-
plished through a 3–wire serial port interface that drives
an internal control logic unit. The 3–wire serial interface
consists of the three input signals: RST, CLK, and DQ.
The RST control signal s used to enable the 3–wire serial
port operation of the device. The RST signal is an active
high input and is required to begin any communication to
the DS1267. The CLK signal input is used to provide tim-
ing synchronization for data input and output. The DQ
signal line is used to transmit potentiometer wiper set-
tings and the stack select bit configuration to the 17–bit
I/O shift register of the DS1267.
Figure 9(a) presents the 3–wire serial port protocol. As
shown, the 3–wire port is inactive when the RST signal
input is low. Communication with the DS1267 requires
the transistion of the RST input from a low state to a high
state. Once the 3–wire port has been activated, data is
entered into the part on the low to high transistion of the
CLK signal inputs. Three–wire serial timing require-
ments are provided in the timing diagrams of Figure
9(b),(c).
Data written to the DS1267 over the 3–wire serial inter-
face is stored in the 17–bit I/O shift register (see
Figure 2). The 17–bit I/O shift register contains both
8–bit potentiometer wiper position values and the stack
select bit. The composition of the I/O shift register is
presented in Figure 2. Bit 0 of the I/O shift register con-
tains the stack select bit. This bit will be discussed in the
section entitled Stacked Configuration. Bits 1 through 8
of the I/O shift register contain the potentiometer–1 wiper
position value. Bit 1 will contain the MSB of the wiper set-
ting for potentiometer–1 and bit 8 the LSB for the wiper
setting. Bits 9 through 16 of the I/O shift register contain
the value of the potentiometer–0 wiper position with the
MSB for the wiper position occupying bit 9 and the LSB bit
16.
DS1267 BLOCK DIAGRAM
Figure 1
RST
CLK
256–1 MULTIPLEXER
L0
H0
256–1 MULTIPLEXER
L1
H1
WIPER–0 8 BITS
WIPER–1 8 BITS
W0
W1
S
OUT
STACK
MULTIPLEXER
CONTROL
LOGIC
b0
b16
C
OUT
DQ
17–BIT I/O SHIFT REGISTER
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