參數(shù)資料
型號: DS1267
廠商: Maxim Integrated Products, Inc.
元件分類: 數(shù)字電位計
英文描述: Dual Digital Potentiometer Chip(雙路數(shù)字電位器芯片)
中文描述: ±5V、雙路、數(shù)字電位器芯片
文件頁數(shù): 3/11頁
文件大?。?/td> 110K
代理商: DS1267
DS1267
022698 3/11
I/O SHIFT REGISTER
Figure 2
b8
b1
POTENTIOMETER–1
b16
b9
POTENTIOMETER–0
b0
17–BIT I/O SHIFT REGISTER
STACK SELECT BIT
Transmission of data always begins with the stack select
bit followed by the potentiometer–1 wiper position value
and lastly the potentiometer–0 wiper position value.
When wiper position data is to be written to the DS1267,
17 bits (or some integer multiple) of data should always
be transmitted. Transactions which do not send a com-
plete 17–bits (or multiple) will leave the register incom-
plete and possibly an error in the desired wiper positions.
After a communication transaction has been completed
the RST signal nput should be taken to a low state to pre-
vent any inadvertent changes to the device shift register.
Once RST has reached a low state, the contents of the
I/O shift register are loaded into the respective multiplex-
ers for setting wiper position. A new wiper position will
only engage after a RST transition to the inactive state.
On device power–up the DS1267 wiper positions will be
set at 50% of the total resistance or binary value 1000
0000.
STACKED CONFIGURATION
The potentiometers of the DS1267 can be connected in
series as shown in Figure 3. This is referred to as the
stacked configuration and allows the user to double the
total end–to–end resistance of the part. The resolution of
the combined potentiometers will remain the same as a
single potentiometer but with a total of 512 wiper posi-
tions available. Device resolution is defined as Rtot/256
(per potentiometer); where Rtot equals the total poten-
tiometer resistance.
The wiper output for the combined stacked potentiome-
ter will be taken at the S
OUT
pin, which is the multiplexed
output of the wiper of potentiometer–0 (W0) or potentiom-
eter–1 (W1). The potentiometer wiper selected at the
S
OUT
output is governed by the setting of the stack select
bit (bit 0) of the 17–bit I/O shift register. If the stack select
bit has value 0, the multiplexed output, S
OUT
, will be that
of the potentiometer–0 wiper. If the stack select bit has
value 1, the multiplexed output, S
OUT
, will be that of the
potentiometer–1 wiper.
STACKED CONFIGURATION
Figure 3
S
OUT
STACK
MULTIPLEXER
W0
W1
H1
L1
H0
L0
POTENTIOMETER–1
POTENTIOMETER–0
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